TTRN012G7 데이터 시트보기 (PDF) - Agere -> LSI Corporation
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TTRN012G7
Agere -> LSI Corporation
TTRN012G7 Datasheet PDF : 22 Pages
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TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
Preliminary Data Sheet
August 2000
Functional Overview (continued)
Clock Synthesizer Operation (continued)
Clock Synthesizer Generated Jitter
The clock synthesizer’s generated jitter performance meets the requirements shown in Table 6. These specifica-
tions apply to the jitter generated at the 2.5 GHz clock pins (CK2G5P/N) when the jitter on the reference clock
(REFCLKP/N) is within the specifications given in Table 9 on page 16, and the loop filter components are chosen to
provide a loop bandwidth of 2 MHz.
Table 6. Clock Synthesizer Generated Jitter Specifications
Parameter
Generated Jitter (p-p):
Measured with 12 kHz to 20 MHz Bandpass
Filter
Generated Jitter (rms):
Measured with 12 kHz to 20 MHz Bandpass
Filter
Typical
0.02
Max
(Device)*
0.09
Unit
UIp-p
0.002
0.009 UIrms
* This denotes the device specification for system SONET/SDH compliance when the loop filter in
Table 5 and Figure 3 is used.
Clock Synthesizer Jitter Transfer
The clock synthesizer’s jitter transfer performance meets the requirement shown in Figure 4 when the loop filter
values shown in Table 5 are used.
(2 MHz, 0.1 dB)
0
10
20
30
40
50
60
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 4. Clock Synthesizer Jitter Transfer
100M
5-8062(F)r.1
10
Lucent Technologies Inc.
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