TTRN012G7 데이터 시트보기 (PDF) - Agere -> LSI Corporation

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TTRN012G7

TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer

Agere -> LSI Corporation 

Preliminary Data Sheet

August 2000

Description (continued)

TTRN012G5 and TTRN012G7

Clock Synthesizer, 16:1 Data Multiplexer

RESETN

D0P

D0N

D1P

D1N

TO DIGITAL LOGIC

INVDAT

DATA

RETIME

INVDATN

ENLBDN

LBDP

LBDN

D2G5P

D2G5N

D15P

D15N

PARITYP

PARITYN

CLKMODE

MONAPAP

MONAPAN

CK155P

CK155N

PHADJ[1:0]

EXTADJN

REFCLKP

REFCLKN

LCKLOSSN

PARITY

CHECK

LOAD

01

1

0

0

AUTO

PHASE

ADJUST

MANUAL

1

PHASE

ADJUST

PARITY

REGISTER

DIVIDE

BY 16

ACQUISITION

INDICATOR

PHASE/

FREQ.

DETECTOR

CHARGE

PUMP

VCO

TEST

01

ENCK2G5

CK2G5P

CK2G5N

VALIDP

VALIDN

RREF2

RREF1

TESTN

TSTCKP

TSTCKN

LFP LFN VCP VCN

5-8060(F)r.3

Note: Diagram is representative of device functionality and conceptual signal flow. Internal implementation details may be different than shown.

Figure 1. Functional Block Diagram

Lucent Technologies Inc.

3

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