LH5324500 데이터 시트보기 (PDF) - Sharp Electronics

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LH5324500

CMOS 24M (3M × 8/1.5M × 16) MROM

Sharp Electronics 

LH5324500

CMOS 24M MROM

A20 44

A19 43

A18 2

A17 3

A16 34

A15 35

A14 36

A13 37

A12 38

A11 39

A10 40

A9 41

A8 42

A7 4

A6 5

A5 6

A4 7

A3 8

A2 9

A1 10

A0 11

MEMORY

MATRIX

(3,145,728 x 8)

(1,572,864 x 16)

COLUMN SELECTOR

CE 12

CE

BUFFER

TIMING

GENERATOR

SENSE AMPLIFIER

OE 14

OE

BUFFER

31 D15

29 D14

27 D13

25 D12

22 D11

20 D10

18 D9

16 D8

30 D7

28 D6

26 D5

24 D4

21 D3

19 D2

17 D1

15 D0

BYTE 33

BYTE/WORD

SWITCHOVER

CIRCUIT

ADDRESS

BUFFER

31

23 13 32

A-1

VCC GND

Figure 2. LH5324500 Block Diagram

5324500-2

PIN DESCRIPTION

SIGNAL

A–1 – A20

D0 – D15

BYTE

CE

PIN NAME

Address input

Data output

Byte/word mode switch

Chip Enable input

NOTE

1

1

1

SIGNAL

OE

VCC

GND

NC

PIN NAME

Output Enable input

Power supply (+5 V)

Ground

No connection

NOTE

NOTE:

1. The D15/A–1 pin becomes LSB address input (A–1) when the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to

be HIGH in word mode. When the address inputs become ’High’ to both A19 and A20, the data outputs become ‘Unspecified’

since the data does not exist in this address area.

2

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