HT62L256-28TSOP-A 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT62L256-28TSOP-A Datasheet PDF : 10 Pages
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Preliminary
HT62L256
A.C. Characteristics
Symbol
Parameter
Read cycle
tRC
Read Cycle Time
tAA
Address Access Time
tACS
Chip Selection Access Time
tAOE
Output Enable to Valid Outputs
tCLZ*
Chip Selection to Output in Low-Z
tOLZ*
Output Enabled to Output in Low-Z
tCHZ*
Chip Deselected to Output in High-Z
tOHZ*
Output Disable to Output in High-Z
tOH
Output Hold from Address Change
Write cycle
tWC
Write Cycle Time
tCW
Chip Selection to End of Write
tAS
Address Setup Time
tAW
Address Valid to End of Write
tWP
Write Pulse Width
tWR
Write Recovery Time
tWHZ
Write to Output in High-Z
tDW
Data Valid to End of Write
tDH
Data Hold from End of Write
tOW
Output Active from End of Write
Min.
70
¾
¾
¾
10
5
¾
¾
10
70
60
0
60
50
0
¾
30
0
5
Typ.
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Ta=25°C, VDD=3.0V±10%
Max.
Unit
¾
ns
70
ns
70
ns
35
ns
¾
ns
¾
ns
25
ns
25
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
¾
ns
20
ns
¾
ns
¾
ns
¾
ns
Note:
1. A write cycle occurs during the overlap of a low CS and a low WE
2. OE may be both high and low in a write cycle
3. tAS is specified from CS or WE, whichever occurs last
4. tWP is an overlap time of a low CS and a low WE
5. tWR, tDW and tDH are specified from CS or WE, whichever occurs first
6. tWHZ is specified by the time when DATA OUT is floating and not defined by the output level
7. When the I/O pins are in data output mode, they should not be forced with inverse signals
Rev. 0.00
3
August 15, 2002
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