LH538700AD 데이터 시트보기 (PDF) - Sharp Electronics
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LH538700AD Datasheet PDF : 6 Pages
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LH538700A
PRELIMINARY
CMOS 8M (1M × 8) MROM
FEATURES
• 1,048,576 words × 8 bit organization
• Access time: 100 ns (MAX.)
• Power consumption:
Operating: 550 mW (MAX.)
Standby: 550 µW (MAX.)
• Static operation
• TTL compatible I/O
• Three-state outputs
• Single +5 V power supply
• Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 400-mil TSOP (Type II)
DESCRIPTION
The LH538700A is an 8M-bit mask-programmable
ROM organized as 1,048,576 × 8 bits. It is fabricated
using silicon-gate CMOS process technology.
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
TOP VIEW
A19
1
A16 2
A15 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
D0 13
D1 14
D2 15
GND 16
32 VCC
31 A18
30 A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 D7
20 D6
19 D5
18 D4
17 D3
538700A-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN TSOP (Type II)
TOP VIEW
A19
1
A16 2
A15 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
D0 13
D1 14
D2 15
GND 16
32 VCC
31 A18
30 A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 D7
20 D6
19 D5
18 D4
17 D3
NOTE: Reverse bend available on request.
538700A-2
Figure 2. Pin Connections for TSOP Package
1
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