LH538700AD 데이터 시트보기 (PDF) - Sharp Electronics

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LH538700AD

CMOS 8M (1M × 8) MROM

Sharp Electronics 

LH538700A

PRELIMINARY

CMOS 8M MROM

A19 1

A18 31

A17 30

A16 2

A15 3

A14 29

A13 28

A12 4

A11 25

A10 23

A9 26

A8 27

A7 5

A6 6

A5 7

A4 8

A3 9

A2 10

A1 11

A0 12

CE 22

OE 24

MEMORY

MATRIX

(1,048,576 x 8)

COLUMN SELECTOR

SENSE AMPLIFIER

CE

BUFFER

TIMING

GENERATOR

OE

BUFFER

32 16

VCC GND

OUTPUT BUFFER

13 14 15 17 18 19 20 21

D0 D1 D2 D3 D4 D5 D6 D7

Figure 3. LH538700A Block Diagram

538700A-3

PIN DESCRIPTION

SIGNAL

A0 – A19

D0 – D7

CE

PIN NAME

Address input

Data output

Chip enable input

SIGNAL

OE

VCC

GND

PIN NAME

Output enable input

Power supply (+5 V)

Ground

2

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