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MP7645B 데이터 시트보기 (PDF) - Exar Corporation

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MP7645B Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
WRITE CYCLE TIMING DIAGRAM
CS
WR
DATA IN
(DB0-DB11)
MP7645B
tCS
tCH
tWR
tDH
tDS
VIH
VIL
DATA VALID
VDD
0
VDD
0
VDD
0
APPLICATION NOTES
Refer to Section 8 for Applications Information
MICROPROCESSOR INTERFACING OF THE
MP7645B
The MP7645B can interface directly to both 8- and 16-bit mi-
croprocessors via its 12-bit wide data latch using standard CS
and WR control signals.
A typical interface circuit for an 8-bit processor is shown
(Figure 1.) This arrangement uses two memory addresses, one
for the lower 8 bits of data to the DAC and one for the upper 4 bits
of data into the DAC via the latch.
Figure 2. shows an alternative approach for use with 8-bit
processors which have a full 16-bit wide address bus such as
6800, 8080 and Z80. This technique uses the 12 lower address
lines of the processor addresses bus to supply data to the DAC,
thus each MP7645B connected in this way uses 4k bytes of ad-
dress locations. Data is written to the DAC using a single mem-
ory write instruction. The address field of the instruction is or-
ganized so that the lower 12 bits contain the data for the DAC
and the upper 4 bits contain the address of the 4k block at which
the DAC resides.
A15
A0
CPU
WR
DB7
DB0
ADDRESS BUS
Q0
ADDRESS
DECODE
Q1
CS
LATCH
WR
CS
DB11
DB8
MP7645B
WR
DB7
DB0
8-BIT DATA BUS
Q0 DECODED ADDRESS FOR DAC
Q1 DECODED ADDRESS FOR LATCH
Figure 1. 8-Bit Processor to MP7645B Interface
A15
A0
CPU
WR
4
ADDRESS
DECODE
Q0
16-BIT ADDRESS BUS
DB11
12
DB0
CS MP7645B
WR
DB7
DATA BUS
DB0
Figure 2. Connecting the MP7645B to 8-Bit
Processors via the Address Bus
Rev. 2.00
5

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