CDP68HC68W1 데이터 시트보기 (PDF) - Intersil
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CDP68HC68W1 Datasheet PDF : 9 Pages
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CDP68HC68W1
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +7V
(Voltage Referenced to VSS Terminal)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
Device Dissipation Per Output Transistor . . . . . . . . . . . . . . . 100mW
Maximum
Maximum
Storage Temperature Range (TSTG) .
Lead Temperature (During Soldering)
.
.
.
.
.-65oC
......
to
..
150oC
265oC
At Distance 1/16 ±1/32 in. (1.59 ± 0.79mm)
From Case for 10s Max
TA = Full Package Temperature Range (All Package Types)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
SYMBOL
MIN
CDP68HC68W1, VDD = 5V ±10%, VSS = 0V, TA = -40oC to 85oC
DC Operating Voltage Range
-
4
TYP
-
MAX
UNITS
6
V
Input Voltage Range (Except VT Pin)
VT Pin Output Voltage Threshold
Device Current in “Power Down” Mode, Clock Disabled
Low Level Output Voltage (IOL = 1.6mA)
High Level Output Voltage (IOH = -1.6mA)
Input Leakage Current
Operating Device Current (fCLK = 1MHz)
Clock Input Capacitance
(VIN = 0V, fCLK = 1MHz, TA = 25oC)
VIH
0.7 • VDD
-
VDD+0.3V
V
VIL
-0.3
-
0.3 • VDD
V
VIT
0.4
-
0.15 • VDD
V
IPD
-
-
1
µA
VOL
-
-
0.4
V
VOH
VDD - 0.4V
-
-
V
IIN
-
-
±1
µA
IOPER
-
-
1
mA
CIN
-
-
10
pF
Control Timing
PARAMETER
CDP68HC68W1, VDD = 5V ±10%, VSS = 0V, TA = -40oC to 85oC
Clock Frequency
Cycle Time
Clock to PWM Out
Clock High Time
Clock Low Time
Rise Time (20% VDD to 70% VDD)
Fall Time (70% VDD to 20% VDD)
SYMBOL
MIN
FCLK
DC
tCYC
-
tPWMO
-
tCLKH
50
tCLKL
50
tR
-
tF
-
MAX
UNITS
8.0
MHz
-
ns
125
ns
-
ns
-
ns
100
ns
100
ns
2
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