CDP68HC68W1 데이터 시트보기 (PDF) - Intersil

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CDP68HC68W1

CMOS Serial Digital Pulse Width Modulator

Intersil 

CDP68HC68W1

3. Deselect the chip

New pulse width out begins and PWM goes high when CS is

raised after last SCK pulse (assuming no previous time-out).

PWM then toggles on falling CLK edges.

Resulting output waveform: Control = 00 = Divide-by-1,

frequency = 4;

PW = 1: (1 + 1) (0 + 1) = 2 CLKs high time.

Fr equency = (---0---4---I-+-N----P1----)C--(--L-0---K-+-----1----) = I---N----P----5-C-----L----K--

CDP68HC68W1 Application Example

The following example was written for a system which has

the CDP68HC68W1 connected to the SPI bus of a

CDP68HC05C8B microcontroller. The program sets the W1

to run a divide by 200 frequency with a duty cycle of 30% by

writing to the Control Register, the Frequency Data Register,

and the Pulse Width Data Register. The frequency and pulse

width are then modified. Finally the pulse width is modified

without changing the frequency. The program was assem-

bled using the Intersil HASM 3.0 assembler.

INTERSIL Corporation (c)1990 - 1997

68HC05 Assembler Version 3.0.2

Filename:

W1.LST

Source Created: 01/08/98, 10:36 am

Assembled:

01/08/98, 10:36 am

00001

***********************************************************************

00002

* File:

W1.S

00003

*

Example W1 routines - sets W1 to a divide by

00004

*

200 output with 30% duty cycle

00005

*

00006

* Date:

Thursday, January 8, 1998

00007

***********************************************************************

00008

00009

***********************************************************************

00010

*

Partial Map of CDP68HC05C8B Hardware Registers

00011

***********************************************************************

00012

00013

0000

Section Registers, $0000

00014

0000

PortA ds

1

;Port A

00015

0001

PortB ds

1

;Port B

00016

0002

PortC ds

1

;Port C

00017

0003

PortD ds

1

;Port D

00018

0004

DDRA ds

1

;Port A Data Direction Register

00019

0005

DDRB ds

1

;Port B DDR

00020

0006

DDRC ds

1

;Port C DDR

00021

0007

_Free1 ds

3

;three unused locations

00022

000A

SPCR ds

1

;SPI Control Register

00023 $0006 =

6

SPE

equ

6

;SPI Enable bit

00024 $0004 =

4

MSTR equ

4

;SPI Master Mode bit

00025

000B

SPSR ds

1

;SPI Status Register

00026 $0007 =

7

SPIF equ

7

;SPI Flag bit for ANDs, CMPs, etc.

00027

000C

SPDR ds

1

;SPI Data Register

00028

00029

***********************************************************************

00030

*

CDP68HC68W1 Constants

00031

***********************************************************************

00032

00033 $0000 =

0

W1

equ

0

;W1 is connected to bit 0 of Port A

00034 $0002 =

2

W1_PC equ

2

;Power Control: 1 = power down

00035 $0001 =

1

W1_CD equ

1

;Clock Divider: 1 = divide by 2

00036

00037

00038

***********************************************************************

00039

*

Main Routines

00040

***********************************************************************

00041

00042

0100

Section Code, $0100

00043

00044* [6] 0100 AD37

jsr

Init_W1

;turn on PA0

00045

Set200_30

00046 [5] 0102 1100

bclr W1,PortA

;select W1 (CE is active low)

00047* [6] 0104 AD28

jsr

Set_SPI_Mode ;Setup the 68HC05 SPI control

00048

;to talk to the W1

00049

00050

******* Set Up Control, Frequency, and Pulse Width

00051

00052

SendCommands

00053 [2] 0106 A601

lda

#W1_CD

;set divide by two clock on W1

7

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