CDP68HC68T1M2Z(2006) 데이터 시트보기 (PDF) - Intersil

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CDP68HC68T1M2Z
(Rev.:2006)

CMOS Serial Real-Time Clock With RAM and Power Sense/Control

Intersil 

Static Electrical Specifications At TA = -40°C to +85°C, VDD = VBATT = 5V ±5%, except as noted. (Continued)

CDP68HC68T1

PARAMETER

CONDITIONS

MIN (NOTE 2) TYP

MAX

Standby Current (Note 3)IB

VB = 2.2V

Crystal Operation

32kHz

-

10

12

Input Capacitance CIN

Maximum Rise and Fall Timestr, tf

(Except XTAL Input and POR Pin 10)

VIN = 0, TA = 25°C

-

-

2

-

-

2

Input Voltage (Line Input Pin Only, Power Sense Mode)

0

10

12

VSYS > VBVT

(For VB Not Internally Connected to VDD)

Power-On Reset (POR) Pulse Width

-

1.0

-

100

75

-

NOTES:

2. Typical values are for TA = 25°C and nominal VDD.

3. Clock out (Pin 1) disabled, outputs open circuited. No serial access cycles.

UNITS

µA

pF

µs

V

V

ns

4

FN1547.7

March 17, 2006

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