CDP68HC68T1 데이터 시트보기 (PDF) - Intersil

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CDP68HC68T1

CMOS Serial Real-Time Clock With RAM and Power Sense/Control

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CDP68HC68T1

Static Electrical Specifications At TA = -40°C to +85°C, VDD = VBATT = 5V ±5%, Unless Otherwise Specified. (Continued)

CDP68HC68T1

PARAMETER

SYMBOL

TEST CONDITIONS

TYP

MIN

(Note 2)

MAX UNITS

Operating Current (Note 3)

VDD = 5V, VB = 3V

Crystal Operation

32kHz

1MHz

ID

IB

-

mA

-

0.025 0.015

-

mA

-

0.08 0.15

-

mA

2MHz

-

0.15 0.25

-

mA

4MHz

-

0.3 0.4

-

mA

Standby Current (Note 3)

VB = 2.2V

Crystal Operation

IB

32kHz

-

10

-

µA

Input Capacitance

Maximum Rise and Fall Times

(Except XTAL Input and POR Pin 10)

CIN VIN = 0, TA = +25°C

tr, tf

-

-

-

-

-

2

pF

2

µs

-

µs

Input Voltage (Line Input Pin Only, Power Sense

Mode)

0

10

12

V

VSYS > VBVT

(For VB Not Internally Connected to VDD)

Power-On Reset (POR) Pulse Width

-

1.0

100

75

-

V

-

ns

NOTES:

2. Typical values are for TA = +25°C and nominal VDD.

3. Clock out (Pin 1) disabled, outputs open circuited. No serial access cycles.

Dynamic Electrical Specifications Bus Timing VDD ±10%, VSS = 0VDC, TA = -40°C to +85°C

LIMITS (ALL TYPES)

IDENTIFICATION

NUMBER

PARAMETER

SYMBOL

VDD = 3.3V

MIN

MAX

VDD = 5V

MIN

MAX

1

Chip Enable Setup Time

tEVCV

2

Chip Enable After Clock Hold Time tCVEX

3

Clock Width High

tWH

4

Clock Width Low

tWL

5

Data In to Clock Setup Time

tDVCV

7

Clock to Data Propagation Delay

tCVDV

8

Chip Disable to Output High Z

tEXQZ

11

Output Rise Time

tr

12

Output Fall Time

tf

A

Data in After Clock Hold Time

tCVDX

B

Clock to Data Out Active

tCVQX

C

Clock Recovery Time

tREC

200

-

100

-

250

-

125

-

400

-

200

-

400

-

200

-

200

-

100

-

-

200

-

100

-

200

-

100

-

200

-

100

-

200

-

100

200

-

100

-

-

200

-

100

200

-

200

-

UNITS

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

4

FN1547.8

October 29, 2007

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