W89C840AF 데이터 시트보기 (PDF) - Winbond
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W89C840AF Datasheet PDF : 82 Pages
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W89C840AF
PERRB
SERRB
INTAB
IO/STS
21
O/OD
22
O/OD
111
PCI Parity Error:
Asserted by the current data receiptor. When
W89C840AF acts the bus master, if a data parity error
is detected and the parity error response bit (FCS<6>) is
also set, it will set both bits of FCS<24> and C14<13>
as 1 to terminate the current transaction after the
current data phase is finished. When W89C840AF acts
the target, if a data parity error is detected and the bit
FCS<6> is set, it will assert PERRB only.
System Error:
This pin is asserted with one PCI clock width within
two PCI clocks after an address parity error is detected,
and keeps in high impedance state when idle.
The interrupt function caused by this event is gated by
the bits in FCS register.
W89C840AF will assert SERRB and will set a high to
the Detect Parity Error bit FCS<31> and the Signal
System Erro bit FCS<30> if an address parity error is
detected and SERRB enable bit FCS<8> is previously
set to 1.
The Bus Error Status bit C14<13> will be set to high if
both an address parity error is detected and the parity
error response bit FCS<6> is set to high.
Interrupt A:
INTAB is asserted when any one of unmasked interrupt
bits in C14/CISR is set. It keeps asserted until all of the
unmasked interrupt bits is cleared.
2) Power Managment Interface
Symbol
PWGD
Pin Type
I
Pin
Number
113
PMEB
RMGWKU
O/OD
118
O/OD
110
Pin Description
Power Good
When PWGD=1, W89C840A is put in normal operation
mode.
When PWGD=0, it isolates whole PCI bus except PMEB.
The PCI bus power can be off by operating system.
Power Management Event
The PMEB signal indicates that a power management
event has occurred, i.e. there is a magic packet received in
suspend mode etc. This pin is open drain.
Remote Magic Packet WakeUp
After received magic packet, this output signal
motherboard to execute wakeup process.
Publication Release Date:October 2000
-8 -
Revision 1.01
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