MPD8020 데이터 시트보기 (PDF) - Micrel
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MPD8020 Datasheet PDF : 2 Pages
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MPD8020
Available Macro Cells
• 16 fully floating 100V, 200mA, 10Ω vertical-DMOS FETs
• 16 high-voltage 100V P- and N-channel level shifters
(configured from 32 cross coupled 20mA to 50mA
P- and N-channel pairs)
• 200 CMOS gates in an uncommitted gate array
· over 30 pre-designed logic “templates” of shift
registers, decoders, flip-flops, NAND gates, NOR
gates, etc.
· general purpose op amps, comparators, and Schmitt
triggers, implemented in the gate array
• 12 TTL/CMOS I/O buffers
• 16 logic drivers (with logic enable) for bottom-side
DMOS drive
• 3 configurable op amp/comparator/Schmitt trigger cells
configurable as:
· ground or VCC sensing amplifiers or comparators
· folded cascode high-performance amplifiers
· NPN input amplifiers
· programmable bandwidth/power consumption
amplifiers
• Unity-gain buffer with adaptive bias (to drive large loads
with minimum quiescent current)
• 1.25V bandgap reference plus multiple programmable
outputs up to VCC
• Overtemperature protection circuit with programmable
temperature trip points and hysteresis
• Master bias programming circuit for all the linears
• High-voltage V++ “doubler” for N-channel gate drive
above the +100V VDD supply
• Low-voltage (VCC) pass regulator to drive a local low-
voltage analog and digital power supply from the high-
voltage supply.
• Multiple current mirrors both at high (100V) and low
(15V) levels
• Floating zener clamps, avalanche zeners, references
and Schottky diodes
• Diffusion, diffusion P-well, pinched and poly resistors
• 40pF of on-chip capacitance
• Isolated PNP and NPN transistors
Micrel
Design Resources and Requirements
Supplied by Micrel
• MPD8020 CMOS/DMOS Semicustom High-Voltage
Array data sheet
• MPD8020 Kit Part #1 (Analog SSI and MSI Circuits)
· 40-pin DIP kit parts with 11 commonly used analog
circuits
· Kit Part Part #1 data sheet with specification and
application hints
• MPD8020 Kit Part #2 (Digital SSI and MSI Circuits)
· 40-pin DIP kit parts with 8 revealing digital circuits for
checking speed and digital timing characteristics (also
some ananlog circuits implemented in the gate array)
· Kit Part #2 data sheet with specification and
application hints
• Highly experienced design and applications engineers
on call to discuss how to optimize a complex analog,
digital, and power circuit on one I.C.
Requirements by Micrel
• System block diagram with basic I/O specifications, or…
• Schematic of circuit implemented with analog,
digital,and discrete power transistors plus the I/O
specification, or…
• Breadboard using Micrel kit parts plus “glue” logic and
I/O specification, or…
• Spice and Hi-Low netlists or other compatible computer
generated description and I/O specifications.
Typical Semicustom Design Cycle
The typical design cycle follows exploratory discussions and
contract initiation.
Week
2
8
12
14
16
17
19
20
Activity
Specification and customer interface
Design and customer interface
Electrical and layout computerized checks
Mask generation
Apply ASIC masks to preprocessed wafers
Wafer test
Packaged test units
Final test, QA and ship 25 units
11
1997
11-3
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