TQ1090-MC 데이터 시트보기 (PDF) - TriQuint Semiconductor
부품명
상세내역
제조사
TQ1090-MC Datasheet PDF : 10 Pages
| |||
TQ1090
AC Characteristics
(VDD = +5 V + 5%, TA = 0 °C to +70 °C)
Symbol Input Clock (REFCLK)
t CPWH
t CPWL
t IR
CLK pulse width HIGH
CLK pulse width LOW
Input rise time (0.8 V - 2.0V)
Test Conditions (Figure 3) 1
Figure 4
Figure 4
Min Typ Max Unit
2
---
— ns
2
---
— ns
—
—
2.0 ns
Symbol Output Clocks (Q0–Q10)
Test Conditions (Figure 3) 1
Min Typ Max Unit
t OR,t OF
t PD1 2
t PD2 2
t SKEW1 3
t SKEW2 3
t SKEW3 3
t SKEW4 3
t CYC 4
t JP 5
t JR 5
t SYNC 6
Rise/fall time (0.8 V – 2.0V)
Figure 4
350
CLK ↑ to FBIN ↑ (TQ1090-MC500)
Figure 4
–850
CLK ↑ to FBIN ↑ (TQ1090-MC700)
Figure 4
–1050
Rise–rise, fall–fall (within group)
Figure 5
—
Rise–rise, fall–fall (group-to-group, aligned)
Figure 6 (skew2 takes into account skew1) —
Rise–rise, fall–fall (group-to-group, non-aligned) (skew3 takes into account skews1, 2)
—
Rise–fall, fall–rise
(skew4 takes into account skew3)
—
Duty-cycle Variation
Figure 4
–1000
Period-to-Period Jitter
Figure 4
—
Random Jitter
Figure 4
—
Synchronization Time
—
—
–350
–350
60
75
—
—
0
80
190
10
1400 ps
+150 ps
+350 ps
150 ps
350 ps
650 ps
1200 ps
+1000 ps
200 ps
400 ps
500 µs
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.
Skew 1 is a subset of skew 2. Skew 2 is a subset of skew 3. Skew 3 is a subset of skew 4.
Definition of skew terms:
Rise–rise:
Skew between rising edges (low to high transitions).
Fall–fall:
Skew between falling edges (high to low transitions).
Rise–fall, fall–rise: Skew between rising-to-falling and falling-to-rising edges.
Within a group:
Skew between outputs of the same group (for example, skew among Group A outputs)
Group-to-group:
Skew between outputs of any group (for example, skew between Group A to Group B outputs)
Aligned:
Skew between outputs that are in phase.
Non-aligned:
Skew between outputs that are not in phase.
4. This specification represents the deviation from 50/50 on the outputs.
5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock. tJP is the jitter on the
output with respect to the same output’s previous rising edge.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the
outputs to FBIN.
Figure 3. AC Test Circuit
+5 V
R1
Z
R2
+5 V
R1
Z
R2
Notes:
R1 = 160 Ω
R2 = 71 Ω
Y+Z=X
Y
FBIN Q0
Q1
Q2
•
•
•
•
CLK Q10
50 Ω
X
•
•
•
•
+5 V
R1 +5 V
R2 R1
R2
+5 V
R1
R2
For additional information and latest specifications, see our website: www.triquint.com
5
Share Link: 