TSA1002IFT 데이터 시트보기 (PDF) - STMicroelectronics

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TSA1002IFT

A/D CONVERTER

STMicroelectronics 

TSA1002

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V

Tamb = 25 C (unless otherwise specified)

N

TIMING CHARACTERISTICS

Symbol

Parameter

FS Sampling Frequency

DC Clock Duty Cycle

TC1 Clock pulse width (high)

Test conditions

Min

I GTyp Max

Unit

S0.5

50 Msps

E40

9

50

10

60

%

ns

TC2 Clock pulse width (low)

Tod

Data Output Delay (Fall of Clock 10pF load capacitance

to Data Valid)

D

9

10

5

ns

ns

Tpd Data Pipeline delay

W Ton

Falling edge of OEB to digital

output valid data

E t(s) Toff

Rising edge of OEB to digital

output tri-state

N duc TIMING DIAGRAM

5.5

cycles

1

ns

1

ns

O R te Pro N+3

F bsole N-1

N

N+2

N+1

N+6

N+7

N+8

O T t(s) - O CLK

N roduc OEB

te P DATA

Obsole OUT

Tpd + Tod

Tod

Toff

N-7

N-6

N-5

N-4

N-3

N-2 N-1

Ton

N+1 N+2

DR

HZ state

4/20

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