DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

ADM9240 데이터 시트보기 (PDF) - Analog Devices

부품명
상세내역
제조사
ADM9240 Datasheet PDF : 22 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
ADM9240
Table X. Register 43h, INT Interrupt Mask Register 1 (Power-On Default = 00h)
Bit
Name
0
+2.5 V
1
+VCCP1
2
+3.3 V
3
+5 V
4
Temp
5
Reserved
6
FAN1
7
FAN2
R/W
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
Power-On Default = 0.
A “1” disables the corresponding interrupt status bit for INT interrupt.
A “1” disables the corresponding interrupt status bit for INT interrupt.
Table XI. Register 44h, INT Mask Register 2 (Power-On Default = 00h)
Bit
Name
R/W
Description
0
+12 V
Read/Write
A “1” disables the corresponding interrupt status bit for INT interrupt.
1
VCCP2
2
Reserved
Read/Write
Read/Write
A “1” disables the corresponding interrupt status bit for INT interrupt.
Power-up default set to Low.
3
Reserved
Read/Write
Power-up default set to Low.
4
CI
Read/Write
A “1” disables the corresponding interrupt status bit for INT interrupt.
5
Reserved
Read/Write
Undefined.
6
Reserved
Read/Write
Undefined.
7
RESET Enable
Read/Write
A “1” enables the RESET function in the configuration register.
Table XII. Register 45h, Reserved Compatibility (Power-On Default = 00h)
Bit
Name
0–7
Reserved
R/W
Read/Write
Description
Reserved for Compatibility.
Table XIII. Register 46h, Chassis Intrusion Clear (Power-On Default = 00h)
Bit
Name
R/W
Description
0–6
Reserved
Read/Write
Undefined (Power On Default = 00h)
7
Chassis Int. Clear
Read/Write
A “1” outputs a minimum 20 ms active low pulse on the chassis intrusion
pin. The register bit clears itself after the pulse has been output.
Table XIV. Register 47h, VID0–3/Fan Divisor Register (Power-On Default 0101(VID3–VID0))
Bit
Name
R/W
Description
0–3
VID
Read
The VID[3:0] inputs from processor core power supplies to indicate the
operating voltage (e.g., 1.3 V to 3.5 V).
4–5
FAN1 Divisor
Read/Write
Sets Counter Prescaler for FAN1 Speed Measurement
<5:4> = 00 – Divide by 1
<5:4> = 01 – Divide by 2
<5:4> = 10 – Divide by 4
<5:4> = 11 – Divide by 8
6–7
FAN2 Divisor
Read/Write
Sets Counter Prescaler for FAN2 Speed Measurement
<7:6> = 00 – Divide by 1
<7:6> = 01 – Divide by 2
<7:6> = 10 – Divide by 4
<7:6> = 11 – Divide by 8
–20–
REV. 0

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]