TX4939 데이터 시트보기 (PDF) - Toshiba
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TX4939 Datasheet PDF : 756 Pages
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Toshiba RISC Processor
Index
TX4939
20.4. Registers........................................................................................................................................................... 20-8
20.4.1. SPI Master Control Register (SPMCR) 0xF800 ................................................................................... 20-9
20.4.2. SPI Control Register 0 (SPCR0) 0xF804 .......................................................................................... 20-10
20.4.3. SPI Control Register 1 (SPCR1) 0xF808 ...........................................................................................20-11
20.4.4. SPI Interframe Delay Time Counter (SPFS) 0xF80C.......................................................................... 20-12
20.4.5. SPI Status Register (SPSR) 0xF814................................................................................................. 20-13
20.4.6. SPI Data Register (SPDR) 0xF818 .................................................................................................. 20-14
CHAPTER 21. CIR CONTROLLER............................................................................................................................... 21-1
21.1. Features............................................................................................................................................................ 21-1
21.2. Block Diagram................................................................................................................................................... 21-2
21.3. Functional Description....................................................................................................................................... 21-3
21.3.1. Theory of Operation ................................................................................................................................... 21-3
21.3.2. Signal Muxing ............................................................................................................................................ 21-3
21.4. Register Definition............................................................................................................................................. 21-4
21.4.1. CIR Control/Status Register (CIR_CSR) 0xFC00................................................................................ 21-4
CHAPTER 22. I2C CONTROLLER ............................................................................................................................... 22-1
22.1. Overview ........................................................................................................................................................... 22-1
22.2. I2C Register Definition ...................................................................................................................................... 22-2
22.2.1. I2C Interrupt Control/Status Register (I2C_ICTSR) 0xF900................................................................... 22-3
22.2.2. I2C Transmit/Receive Register (I2C_TXRR) 0xF904 .......................................................................... 22-4
22.2.3. I2C Command Register (I2C_CR) 0xF908 .......................................................................................... 22-4
22.2.4. I2C Prescale Register (I2C_PRE) 0xF90C......................................................................................... 22-5
22.2.5. I2C Control Register (I2C_CTR)
0xF920........................................................................................... 22-6
22.3. System Configuration........................................................................................................................................ 22-7
22.3.1. I2C Protocol ............................................................................................................................................... 22-7
22.3.2. START signal ............................................................................................................................................. 22-7
22.3.3. Slave Address Transfer .............................................................................................................................. 22-7
22.3.4. Data Transfer ............................................................................................................................................. 22-8
22.3.5. STOP signal ............................................................................................................................................... 22-8
22.3.6. Arbitration Procedure ................................................................................................................................. 22-8
22.3.7. Clock Synchronization................................................................................................................................ 22-8
22.3.8. Clock Stretching ......................................................................................................................................... 22-9
22.4. Architecture ....................................................................................................................................................... 22-9
22.5. Clock Generator .............................................................................................................................................. 22-10
22.6. Byte Command Controller............................................................................................................................... 22-10
22.6.1. Byte Mode:............................................................................................................................................... 22-10
22.7. Bit Command Controller.................................................................................................................................. 22-12
22.8. Data IO Shift Register ..................................................................................................................................... 22-12
22.9. Programming Examples.................................................................................................................................. 22-13
22.9.1. Example 1 (Byte Mode)............................................................................................................................ 22-13
22.9.2. Example 2 (Byte Mode)............................................................................................................................ 22-14
CHAPTER 23. I2S CONTROLLER ............................................................................................................................... 23-1
23.1. Overview ........................................................................................................................................................... 23-1
23.2. I2S Function...................................................................................................................................................... 23-3
23.2.1. I2S Interface ............................................................................................................................................... 23-3
23.2.2. Mode of operation ...................................................................................................................................... 23-6
23.2.3. MCLK and SCK Clock................................................................................................................................ 23-7
23.2.4. MCLK and WS Detection ........................................................................................................................... 23-8
23.3. DMA Interface ................................................................................................................................................... 23-9
23.3.1. Overview .................................................................................................................................................... 23-9
23.3.2. DMA Channel Mapping: ........................................................................................................................... 23-10
23.3.3. DMA Operation: ....................................................................................................................................... 23-10
23.4. I2S Register Definition ......................................................................................................................................23-11
23.4.1. Register Definition.....................................................................................................................................23-11
23.4.2. I2S Channel Main Control Register (I2SMCR) 0xFA00 .......................................................................23-11
23.4.3. I2S Channel Control Register (I2SCCR) 0xFA04 .............................................................................. 23-12
23.4.4. I2S Interrupt Control Register (I2SICTRL) 0xFA08............................................................................ 23-14
23.4.5. I2S Clock Option Register (I2SCOR) 0xFA0C.................................................................................. 23-15
23.5. Interface Signals ............................................................................................................................................. 23-17
CHAPTER 24. ACLINK CONTROLLER ....................................................................................................................... 24-1
24.1. Features............................................................................................................................................................ 24-1
24.2. Configuration..................................................................................................................................................... 24-2
Rev. 3.3 May 18, 2007
ix
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