TX4939 데이터 시트보기 (PDF) - Toshiba

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TX4939

64-Bit TX System RISC

Toshiba 

Index

Toshiba RISC Processor

TX4939

27.2.5. Initializing the Extended EJTAG Interface .................................................................................................. 27-4

27.2.6. Features..................................................................................................................................................... 27-5

27.2.7. EJTAG interface ......................................................................................................................................... 27-5

27.2.8. JTAG Interface ........................................................................................................................................... 27-6

27.2.9. Processor Access Overview....................................................................................................................... 27-6

27.2.10. Instruction ................................................................................................................................................ 27-6

27.2.11. Debug Unit ............................................................................................................................................... 27-7

27.2.12. Register Map............................................................................................................................................ 27-7

27.3. Processor Bus Break Function.......................................................................................................................... 27-8

27.4. Debug Exception............................................................................................................................................... 27-8

27.4.1. Debug Single Step (DSS)........................................................................................................................... 27-8

27.4.2. Debug Breakpoint exception (Dbp) ............................................................................................................ 27-8

27.4.3. JTAG Break Exception ............................................................................................................................... 27-8

27.4.4. Debug Exception Handling......................................................................................................................... 27-8

27.4.5. Branching to debug handler ....................................................................................................................... 27-8

27.4.6. Exception handling when in Debug Mode (DM bit is set) ........................................................................... 27-8

27.5. Real Time PC TRACE Output ........................................................................................................................... 27-8

CHAPTER 28. ELECTRICAL CHARACTERISTICS ..................................................................................................... 28-1

28.1. Absolute Maximum Rating ................................................................................................................................ 28-1

28.2. Recommended Operating Conditions ............................................................................................................... 28-1

28.3. DC Characteristics ............................................................................................................................................ 28-2

28.3.1. DC Characteristics of Pins (Except PCI I/F)............................................................................................... 28-2

28.3.2. DC Characteristics of Pins (PCI I/F) .......................................................................................................... 28-3

28.4. AC Characteristics............................................................................................................................................. 28-4

28.4.1. MSTCLK, MSTCLK2 AC Characteristics.................................................................................................... 28-4

28.4.2. Power ON AC Characteristics .................................................................................................................... 28-4

28.4.3. DDR SDRAM Interface AC Characteristics ................................................................................................ 28-5

28.4.4. External Bus Interface AC Characteristics ............................................................................................... 28-10

28.4.5. PCI Interface AC Characteristics...............................................................................................................28-11

28.4.6. AC-link Interface AC characteristics ......................................................................................................... 28-13

28.4.7. SPI AC characteristics ............................................................................................................................. 28-14

28.4.8. AC characteristics of ATA Interface .......................................................................................................... 28-15

28.4.9. Ethernet Interface (RMII) AC characteristics ............................................................................................ 28-20

28.4.10. AC Characteristics of Video Port ............................................................................................................ 28-22

CHAPTER 29. PACKAGE OUTER APPEARANCE...................................................................................................... 29-1

29.1. Package Drawing .............................................................................................................................................. 29-1

29.2. Recommended Motherboard Footprint ............................................................................................................. 29-2

APPENDIX A. GENERAL DIRECTIONS FOR USING THE TX4939 CRYPT ENGINE ..................................................A-1

A.1. Introduction........................................................................................................................................................... A-1

A.2. Terminology Used for the CIPHER Engine ........................................................................................................... A-1

A.3. Overview of the CIPHER Engine .......................................................................................................................... A-2

A.4. Encryption and Hashing Operations ..................................................................................................................... A-4

A.4.1. Initializing the Engine..................................................................................................................................... A-4

A.4.2. Cipher Operation ........................................................................................................................................... A-4

A.4.3. Hashing ......................................................................................................................................................... A-5

A.4.4. Interrupt Servicing ......................................................................................................................................... A-6

A.4.5. Storing the Context ........................................................................................................................................ A-6

A.5. Procedures of Random Number Generation ........................................................................................................ A-7

A.5.1. Initializing the RNG ........................................................................................................................................ A-7

A.5.2. Using the RNG .............................................................................................................................................. A-7

A.5.3. Using the Interrupt Function .......................................................................................................................... A-7

A.6. Encryption and Hashing Using Chained Descriptors ............................................................................................ A-8

A.6.1. Block Sizes of the Descriptor and Algorithms ................................................................................................ A-8

A.6.2. Using Control Flags ....................................................................................................................................... A-8

A.6.3. Algorithms That Allow the Use of Chained Descriptors.................................................................................. A-8

A.6.4. Examples of the Allowable Chained Descriptors ........................................................................................... A-9

APPENDIX B. REVISION ................................................................................................................................................B-1

Rev. 3.3 May 18, 2007

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