UC1608XFAC 데이터 시트보기 (PDF) - Unspecified

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UC1608XFAC

128x240 Matrix LCD Controller-Drivers

Unspecified 

ULTRACHIP

High-Voltage Mixed-Signal IC

©1999-2002

DISPLAY DATA RAM

DATA ORGANIZATION

The display data is 1-bit per pixel and stored in a

dual port static RAM (RAM, for Display Data RAM).

The RAM size is 128x240 for UC1608. This array

of data bits is further organized into pages of 8 bit

slices to facilitate parallel bus interface.

When Mirror X (MX, LC[2]) is OFF, the 1st column

of LCD pixels will correspond to the bits of the first

byte of each page, the 2nd column of LCD pixels

correspond to the bits of the second byte of each

page, etc.

MSB FIRST OR LSB FIRST

There are two options to map D[7:0] to RAM, MSB

first (MSF=1), or LSB first (MSF=0), as illustrated in

next page.

DISPLAY DATA RAM ACCESS

The memory used in UC1608 Display Data RAM

(RAM) is a special purpose dual port RAM which

allows asynchronous access to both its column and

row data. Thus, RAM can be independently

accessed both for Host Interface and for display

operations.

DISPLAY DATA RAM ADDRESSING

A Host Interface (HI) memory access operation

starts with specifying Page Address (PA) and

Column Address (CA) by issuing Set Page Address

and Set Column Address commands.

If wrap-around (WA, AC[0]) is OFF (0), CA will stop

increasing after reaching the end of page (239),

and system programmers need to set the values of

PA and CA explicitly.

If WA is ON (1), when CA reaches end of page, CA

will be reset to 0 and PA will increment or

decrement, depending on the setting of Page

Increment Direction (PID, AC[2]). When PA

reaches the boundary of RAM (i.e. PA = 0 or 19),

PA will be wrapped around to the other end of RAM

and continue.

20

Revision 0.52

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