UJA1069 데이터 시트보기 (PDF) - NXP Semiconductors.

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UJA1069

LIN fail-safe system basis chip

NXP Semiconductors. 

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

mode change via SPI

mode change via SPI

watchdog

trigger

Standby mode

V1: ON

SYSINH: HIGH

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

mode change via SPI

watchdog

trigger

Normal mode

V1: ON

SYSINH: HIGH

LIN: all modes available

watchdog: window

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

wake-up detected with its wake-up interrupt disabled

mode change via SPI

OR mode change to Sleep with pending wake-up

OR watchdog time-out with watchdog timeout interrupt disabled

OR watchdog OFF and IV1 > IthH(V1) with reset option

OR interrupt ignored > tRSTN(INT)

OR RSTN falling edge detected

flash entry enabled (111/001/111 mode sequence)

OR mode change to Sleep with pending wake-up

OR V1 undervoltage detected

OR illegal Mode register code

OR watchdog not properly served

OR interrupt ignored > tRSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

Sleep mode

V1: OFF

SYSINH: HIGH/float

LIN: off-line

watchdog: time-out/OFF

INH/LIMP: LOW/float

RSTN: LOW

EN: LOW

init Normal mode

via SPI successful

Restart mode

V1: ON

SYSINH: HIGH

LIN: off-line

watchdog: start-up

INH/LIMP: LOW/float

EN: LOW

init Normal mode

via SPI successful

supply connected

for the first time

Start-up mode

V1: ON

SYSINH: HIGH

LIN: off-line

watchdog: start-up

INH/LIMP: HIGH/LOW/float

EN: LOW

t > tWD(init)

OR SPI clock count < > 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

wake-up detected

AND oscillator ok

AND t > tret

wake-up detected

OR watchdog time-out

OR V3 overload detected

init Flash mode via SPI

AND flash entry enabled

leave Flash mode code

OR watchdog time-out

OR interrupt ignored > tRSTN(INT)

OR RSTN falling edge detected

OR V1 undervoltage detected

OR illegal Mode register code

t > tWD(init)

OR SPI clock count < > 16

OR RSTN falling edge detected

OR RSTN released and V1 undervoltage detected

OR illegal Mode register code

watchdog

trigger

Flash mode

V1: ON

SYSINH: HIGH

LIN: all modes available

watchdog: time-out

INH/LIMP: HIGH/LOW/float

EN: HIGH/LOW

Fail-safe mode

V1: OFF

SYSINH: HIGH/float

LIN: off-line

watchdog: OFF

INH/LIMP: LOW

RSTN: LOW

EN: LOW

oscillator fail

OR RSTN externally clamped HIGH detected > tRSTN(CHT)

OR RSTN externally clamped LOW detected > tRSTN(CLT)

OR V1 undervoltage detected > tV1(CLT)

from any

mode

001aad670

Fig 4. Main state diagram

UJA1069_4

Product data sheet

Rev. 04 — 28 October 2009

© NXP B.V. 2009. All rights reserved.

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