UPA1772 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPA1772 Datasheet PDF : 6 Pages
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µPA1772
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = −30 V, VGS = 0 V
−1 µA
Gate Leakage Current
Gate Cut-off Voltage Note
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
IGSS
VGS(off)
| yfs |
RDS(on)1
VGS = m20 V, VDS = 0 V
VDS = −10 V, ID = −1 mA
VDS = −10 V, ID = −4 A
VGS = −10 V, ID = −4 A
m10 µA
−1.0 −1.7 −2.5 V
6
12
S
17.4 20.0 mΩ
RDS(on)2 VGS = −4.5 V, ID = −4 A
23.5 29.5 mΩ
RDS(on)3 VGS = −4.0 V, ID = −4 A
25.8 34.0 mΩ
Input Capacitance
Ciss
VDS = −10 V
1500
pF
Output Capacitance
Coss
VGS = 0 V
550
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
240
pF
Turn-on Delay Time
td(on)
VDD = −15 V, ID = −4 A
13
ns
Rise Time
tr
VGS = −10 V
11
ns
Turn-off Delay Time
td(off)
RG = 10 Ω
120
ns
Fall Time
tf
70
ns
Total Gate Charge
QG
VDD = −24 V
34
nC
Gate to Source Charge
QGS
VGS = −10 V
5
nC
Gate to Drain Charge
QGD
ID = −8 A
9
nC
Body Diode Forward Voltage
VF(S-D) IF = 8 A, VGS = 0 V
0.84 1.2 V
Reverse Recovery Time
trr
IF = 8 A, VGS = 0 V
50
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A/µs
37
nC
Note Pulsed: PW ≤ 350 µs, Duty cycle ≤ 2%
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
RG
PG.
VGS(−)
0
τ
τ = 1µs
Duty Cycle ≤ 1%
RL
VDD
VGS(−)
VGS
Wave Form
10%
0
VDS(−)
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off)
tf
ton
toff
D.U.T.
IG = −2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet G15830EJ1V0DS
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