UPD16602N 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD16602N

312-OUTPUT TFT-LCD FULL COLOR DRIVER

NEC => Renesas Technology 

µPD16602

3. PIN DESCRIPTION

Pin Symbol

S1 to S312

CLK

DR0 to DR3

DG0 to DG3

DB0 to DB3

R/L

SPR

SPL

Note

PL/NL

S/D

Note

HS

LPC

BIAS1

BIAS2

VDD1

VDD2(D)

VDD2(A)

VCOM

VSS1

VSS2(D)

VSS2(A)

VSS2(C)

TEST

Pin Name

Driver outputs

Clock input

Analog display

signal inputs

Description

Output pins for sampled analog image signals. When driven with VDD2 = 12.5 V, a

11.5 VP-P analog voltage whose input/output characteristic is gain 1 is output.

This pin reads the start pulse at the rising of CLK and starts sampling of analog

display signals in 12 channels simultaneously. The active edges of CLK are all

rising edges.

Analog image signal input pins. Please input analog display signals by inverting the

polarity for each display line.

Shift direction

switching input

Start pulse input/

output

Start pulse input/

output

Polarity inversion

input

Arrangement

switching input

Horizontal

synchronous input

Low power control

input

Bias voltage inputs

Logic power supply

Driver power supply

Driver power supply

Common power

supply

Logic ground

Driver ground

Driver ground

Driver ground

Test pin

The shift direction of the shift register is as follows.

R/L = H (right shift) ; SPR input, S1 → S312, SPL output

R/L = L (left shift) ; SPL input, S312 → S1, SPR output

R/L = H (right shift) ; start pulse input pin

R/L = L (left shift) ; start pulse output pin

R/L = H (right shift) ; start pulse output pin

R/L = L (left shift) ; start pulse input pin

S/D = L; When PL/NL = H, Both odd number pin and even number pin samples

negative analog display signals and outputs positive analog signals from the

driver output.

When PL/NL = L, Both odd number pin and even number pin samples

positive analog display signals and outputs negative analog signals from the

driver output.

S/D = H; When PL/NL = H, Odd number pin samples negative analog display signals

and outputs positive analog signals from the driver output. Even number pin

samples positive analog display signals and outputs negative analog signals

from the driver output.

When PL/NL = L, Odd number pin samples positive analog display signals

and outputs negative analog signals from the driver output. Even number pin

samples negative analog display signals and outputs positive analog signals

from the driver output.

S/D = H; Complying with one side arrangement dot inverting.

S/D = L; Complying with both sides arrangement dot inverting.

This pin shuts off the output at the falling edge and then outputs analog display

signals at the rising. When HS = L, after the driver output pin goes to high impedance

this pin switches PL/NL and resets the internal hold capacity and output buffer to the

VCOM level.

This pin shuts off the output buffer low current supply and increases the output

impedance. The LPC = “H” mode allows the static current consumption to be

reduced by approximately 20 %.

These pins control the current consumption of the output buffer by applying a

stabilized external power supply.

3.3 V ±0.3 V

13.5 VMAX.

13.5 VMAX.

This pin applies the intermediate voltage of a stable LCD drive voltage from a voltage

follower, etc.

Logic ground

High voltage block (level shifter)

High voltage block (output buffer)

High voltage block (sample & hold)

“L” or left open

Note Sample & hold operation and reset operation of the output buffer capacitance and VCOM level are performed

by the PL/NL and HS logic.

5

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