UPD16602N 데이터 시트보기 (PDF) - NEC => Renesas Technology

부품명

상세내역

제조사

UPD16602N

312-OUTPUT TFT-LCD FULL COLOR DRIVER

NEC => Renesas Technology 

µPD16602

4. NOTES ON USE

(1) In order to prevent latch up breakdown, power should be applied in the order of:

VDD1 → logic input → VDD2(D), (A) → VBIAS1,2, VCOM → analog display signal input, and turned off in the reverse

order.

This order should also be observed in transition periods.

(2) VSS1, VSS2(D), VSS2(A) and VSS2(C) are connected in the diffusion layer, but also be sure to connect them

externally.

Do not share the sample & hold ground VSS2(C) with other ground wiring on the mount board, but connect it to

the edge to the signal board. There is a possibility of high-voltage or logic type noise being superimposed

onto the sample & hold circuit, damaging the analog characteristics (output deviation, etc.).

(3) Likewise, to prevent the sample & hold characteristics from deteriorating, insert a bypass capacitor of 0.1 µF

between VDD1 and VSS1, and approximately 0.1 µF between VDD2(D), (A) and VSS2(D), (A). An unstable power

supply may cause a driver through current, preventing the output range of the output buffer from being

sufficiently secured. Therefore, determine the capacitance of the bypass capacitor after a thorough

evaluation.

(4) When LPC = “H”, stable current supply of the output buffer may be shut off, which will impede normal

negative feedback, and when the LCD panel load is small, the output voltage may become abnormal.

Normal operation is assured with approximately 10 kΩ + 50 pF, but when the time constant is smaller than

this, please set LPC = “L”.

(5) Data input/output relationship

As shown below, irrespective of right shift and left shift.

Output

S1

S2

S3

S4

S5

S6

Data

DR0

DB0

DG0

DR1

DB1

DG1

S309

DG2

S310

DR3

S311

DB3

S312

DG3

(6) Bias control method

Externally applying a voltage to pins BIAS1 and BIAS2 can control the output buffer current consumption. In

this case, the analog characteristics (output deviation, driving capability, response speed, etc.) will not

change. Please refer to the configuration in the figure below for the actual circuit. Also refer to the same

configuration for the VCOM voltage input circuit. Current per driver IC is as follws.

VDD2

100 µAMIN.

(per IC)

VBIAS1, VBIAS2, VCOM

0.01 µF

6

Share Link: