UPD16602N 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD16602N Datasheet PDF : 16 Pages
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µPD16602
5. FUNCTIONAL DESCRIPTION
(1) Input Specification of the analog display signal (n = 0 to 25, R/L = “H” or “L”)
Display signal input terminal/Output terminal
S/D PL/NL
DR0
S12n + 1
DB0
S12n + 2
DG0
S12n + 3
DR1
S12n + 4
---
DG2
S12n + 9
DR3
S12n + 10
DB3
S12n + 11
DG3
S12n + 12
H
H
(–)
(+)
(–)
(+)
---
(–)
(+)
(–)
(+)
L
(+)
(–)
(+)
(–)
---
(+)
(–)
(+)
(–)
L
H
(–)
(–)
(–)
(–)
---
(–)
(–)
(–)
(–)
L
(+)
(+)
(+)
(+)
---
(+)
(+)
(+)
(+)
(+) : Please input the positive analog input signal.
(–) : Please input the negative analog input signal.
(2) Output Specification of the analog display signal
• Single Bank Arrangement for dot inversion (S/D = “H”)
Polarity of the output voltage
Line No.
PL/NL
S1 (DR0) S2 (DR0) S3 (DG0) S4 (DR1) S5 (DB1) S6 (DG1) S7 (DR2)
⋅⋅⋅
1
H
(+)
(–)
(+)
(–)
(+)
(–)
(+)
⋅⋅⋅
2
L
(–)
(+)
(–)
(+)
(–)
(+)
(–)
⋅⋅⋅
3
H
(+)
(–)
(+)
(–)
(+)
(–)
(+)
⋅⋅⋅
4
L
(–)
(+)
(–)
(+)
(–)
(+)
(–)
⋅⋅⋅
5
H
(+)
(–)
(+)
(–)
(+)
(–)
(+)
⋅⋅⋅
(+) : Positive analog output (Negative line sampling), (–) : Negative analog output (Positive line sampling)
• Dual Bank Arrangement for dot inversion (S/D = “L”)
Polarity of the each output voltage
Input signal polarity
Output Polarity of the upper driver IC’s
Line No.
PL/NL
Upper side Lower side
S1
(DR0)
S2
(DB0)
S3
(DG0)
S4
(DR1)
1
H
L
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
2
L
H
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
3
H
L
(+)
(–)
(+)
(–)
(+)
(–)
(+)
(–)
4
L
H
(–)
(+)
(–)
(+)
(–)
(+)
(–)
(+)
767
H
768
L
L
(+)
H
(–)
Sn : Output voltage of the upper side driver,
Sn’ : Output voltage of the lower side driver,
(–)
(+)
(–)
(+)
(–)
(+)
(+)
(–)
(+)
(–)
(+)
(–)
S312’
S311’
S310’
(DG3’)
(DB3’)
(DR3’)
Output polarity of the lower driver IC’s
(+) : Positive output of the upper side driver
(–) : Negative output of the lower side driver
(–)
(+)
S309’
(DG2’)
7
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