UPD16650N 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD16650N

120-/128-OUTPUT TFT-LCD GATE DRIVER

NEC => Renesas Technology 

µPD16650

CAUTIONS FOR USE

1) Power-on sequence

To prevent latch-up disruption, the power must be switched on in the order:

VCC → VEE1 → VEE2 → VDD → Logic input

When witching off, reverse the order. This order must be observed also during transition.

2) Insertion of bypass capacitors

The internal logic circuit operates at a high voltage. To make VIH and VIL immune to noise, use capacitors of

0.1 µF or so between supply voltages as shown below.

VDD

VCC

0.1µ F

0.1µ F

VSS

VEE2

0.1µ F

3) Negative voltage level shift

If it is necessary to shift the level of a negative supply voltage, shift the VEE1 (driver supply voltage) level. The

shift should be limited to within: VEE2 ≤ VEE1 ≤ VEE2 + 10 V

Note that shifting the VEE1 level results in the ON-state output resistance and output fall time ratings being

changed.

4) Handling the VEE1 and VEE2 driver negative supply voltage pins

For applications in which a negative supply voltage level is not shifted, connect the VEE1 pin (driver supply voltage)

to the VEE2 pin (logic supply voltage) outside the TCP. Fix all unused input pins to the VEE2 level.

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