UPD16650N 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD16650N Datasheet PDF : 12 Pages
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µPD16650
SWITCHING CHARACTERISTICS
(TA = –20 °C to +70 °C, VDD = 20 V, VEE1 = VEE2 = –20 V, VSS = 0 V, VCC = 3.3 ±0.3 V or 5.0 ±0.5 V)
Parameter
STVR and STVL output delay
Driver output delay
Output rise time
Output fall time
Input capacitance
Maximum clock frequency
Symbol
tPHL1
tPLH1
tPHL2
tPLH2
td1
td2
tTHL
tTLH
CI
fφX
Conditions
CL = 20 pF
CLK → STVR(STVL)
CL = 220 pF
CLK → Xn
CL = 220 pF, OE: L → H
CL = 220 pF, OE: H → L
CL = 220 pF
CL = 220 pF
TA = 25 °C
For cascade connection
Min.
Typ.
Max.
Unit
600
ns
600
ns
700
ns
700
ns
700
ns
700
ns
300
ns
300
ns
15
pF
100
kHz
TIMING REQUIREMENTS
(TA = –20 °C to +70 °C, VDD = 20 V, VEE1 = VEE2 = –20 V, VSS = 0 V, VCC = 3.3 ±0.3 V or 5.0 ±0.5 V)
Parameter
Clock pulse high width
Clock pulse low width
Data setup time
Data hold time
Symbol
PWφX(H)
PWφX(L)
tsetup
thold
Conditions
Duty = 50 %
Duty = 50 %
STVR(STVL) ↑ → CLK ↑
CLK ↑ → STVR(STVL) ↓
Min.
Typ.
Max.
Unit
500
ns
500
ns
100
ns
100
ns
Remark The logic input rise time (tr) and fall time (tf) must be within 20 ns (between 10 % and 90 % of the peak
amplitude of the input).
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