UPD16647N 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD16647N Datasheet PDF : 16 Pages
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µ PD16647
3. PIN DESCRIPTION
Pin Symbol
S1 to S402/384
Pin Name
Driver output
D00 to D05
D10 to D15
D20 to D25
R,/L
Display data input
Shift direction select input
STHR
STHL
Bcont
Right shift start pulse I/O
Left shift start pulse I/O
Bias control
CLK
Shift clock input
STB
Latch input
Osel
Selection of number of outputs
V0 to V9
γ-corrected power supply
INV
VDD1
VDD2
VSS1
VSS2
Data inversion input
Logic circuit power supply
Driver circuit power supply
Logic ground
Driver ground
Description
Output 64 gray-scale analog voltages converted from digital signals.
Osel = H or open: 402 outputs (S1 to S402/384)
Osel = L : 384 outputs (S1 to S192, S211/193 to S402/384)
S193 to S210 outputs are invalid in 384 outputs.
Inputs 18-bit-wide display gray scale data (6 bits) x 3 dots (RGB).
DX0 : LSB, DX5 : MSB
This pin inputs/outputs start pulses in cascade mode.
Shift direction of shift register is as follows:
R,/L = H : STHR input, S1 → S402, STHL output
R,/L = L : STHL input, S402 → S1, STHR output
R,/L = H : Inputs start pulse
R,/L = L : Outputs start pulse
R/L = H : Outputs start pulse
R/L = L : Inputs start pulse
This pin can be used to finely control the bias current inside the output
amplifier. In cases when fine-control is necessary, connect this pin to VDD2
using a resistor of 10 to 100kΩ (per IC). When this fine-control function is
not required, short-circuit this pin to VDD2. Refer to 7. Bias Current Control
Function/Bcont.
Inputs shift clock to shift register. Display data is loaded to data register at
rising edge of this pin. Start pulse output goes high at rising edge of 134th
clock after start pulse has been input, and serves as start pulse to driver in
next stage. 134th clock of driver in first stage serves as start pulse of driver
in next stage.
Contents of data register are latched at rising edge, transferred to D/A
converter, and output as analog voltage corresponding to display data.
Contents of internal shift register are cleared after STB has been input. One
pulse of this signal is input when µ PD16647 is started, and then device
operates normally.
For STB input timing, refer to 9. Switching Characteristics Waveform.
Selects number of outputs. This pin is internally pulled up to VDD1.
Osel = H or open : 402 outputs (S1 to S402/384)
Osel = L : 384 outputs (S1 to S192, S211/193 to S402/384)
Inputs γ-corrected power from external source.
VSS2 ≤ V9 ≤ V8 ≤ V7 ≤ V6 ≤ V5 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0 ≤ VDD2 or
VSS2 ≤ V0 ≤ V1 ≤ V2 ≤ V3 ≤ V4 ≤ V5 ≤ V6 ≤ V7 ≤ V8 ≤ V9 ≤ VDD2
Maintain gray scale power supply during gray scale voltage output.
Input data can be inverted when display data is loaded.
INV = H : Inverts and loads input data.
INV = L : Does not invert input data.
3.3 V ± 0.3 V
5.0 V ± 0.5 V
Ground
Ground
Caution Be sure to turn on power in the order VDD1, logic input, VDD2, and gray scale power (V0 to V9), and
turn off power in the reverse order, to prevent the µ PD16647 from being damaged by latchup. Be
sure to observe this power sequence even during a transition period.
4
Data Sheet S13607EJ2V0DS00
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