UPD16716 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD16716

384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES)

NEC => Renesas Technology 

µ PD16716

4. PIN FUNCTIONS

(1/2)

Pin Symbol

Pin Name

I/O

Description

S1 to S384

Driver

O

The D/A converted 64-gray-scale analog voltage is output.

D00 to D05

D10 to D15

D20 to D25

Display data

I

The display data is input with a width of 36 bits, viz., the gray scale data (6 bits)

by 6 dots (2 pixels).

DX0: LSB, DX5: MSB

D30 to D35

D40 to D45

D50 to D55

R,/L

 STHR

Shift direction

control

Right shift start

pulse

I

Refers to the shift direction control. The shift directions of the shift registers are

as follows.

R,/L = H : STHR input, S1 → S384, STHL output

R,/L = L : STHL input, S384 → S1, STHR output

I/O These refer to the start pulse I/O pins when driver ICs are connected in cascade.

Loading of display data starts when H is read at the rising edge of CLK.

R,/L = H (right shift): STHR input, STHL output

 STHL

R,/L = L (left shift): STHL input, STHR output

Left shift start pulse I/O

A high level should be input as the pulse of one cycle of the clock signal.

If the start pulse input is more than 2CLK, the first 1CLK of the high-level input is

valid.

CLK

Shift clock

I

Refers to the shift register’s shift clock input. The display data is loaded into the

data register at the rising edge.

At the rising edge of the 64th clock after the start pulse input, the start pulse

output reaches the high level, thus becoming the start pulse of the next-level



driver. If 66-clock pulses are input after input of the start pulse, input of display

data is halted automatically. The contents of the shift register are cleared at the

STB’s rising edge.

STB

Latch

I

The contents of the data register are transferred to the latch circuit at the rising

edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It

is necessary to ensure input of one pulse per horizontal period.

POL

Polarity

 POL21, POL22 Data inversion

I

POL = L : The S2n–1 output uses V0 to V4 as the reference supply. The S2n output

uses V5 to V9 as the reference supply.

POL = H : The S2n–1 output uses V5 to V9 as the reference supply. The S2n output

uses V0 to V4 as the reference supply.

S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL

signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.

I Data inversion can invert when display data is loaded.

POL21: Invert/not invert of display data D00 to D05, D10 to D15, D20 to D25.

POL22: Invert/not invert of display data D30 to D35, D40 to D45, D50 to D55.

POL21, POL22 = H : Display data is inverted.

POL21, POL22 = L : Display data is not inverted.

LPC

Low power control

I

The current consumption is lowered by controlling the constant current source of

the output amplifier. This pin is pulled up to the VDD1 power supply inside the IC.

In low power mode (LPC = L), the static current consumption of VDD2 reduced to

about 2/3 of the normal current consumption.

LPC = H or Open : Normal power mode

LPC = L : Low power mode

4

Data Sheet S14417EJ1V1DS

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