UPD161830 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD161830 Datasheet PDF : 24 Pages
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µPD161830
4.1 Drive Timing by MODE and AP Signal
·MODE = L
Normal drive is selected when a MODE pin is set as L.
Based on output stage construction, AP pin, STB pin, CLK pin signal, and the relation of Sn (sauce output) state are
shown in the next figure.
From 1 clock of a CLK signal to 4 clock is used for the output stage after a STB standup, it carries out decoding to
the latch output voltage level of display data, and transmits to an output circuit.
The output circuit's having prevented from Sn pin output compulsorily the output of the level which is not decided as
a Hi-Z state from the standup of a STB signal to the standup of a CLK signal 4 clock.
When AP pin is L input after 4 clock rises, as for Sn pin output, Hi-Z state is maintained, and an output circuit
changes from the standup of AP pin input to an AMP drive state. Moreover, Sn pin outputs that the notes 1 which pull
up to the voltage (display data) level which requires the potential of a TFT drain line, or are reducedNote1.
When low power consumption is required, AMP pin is switched from H to L, after a voltage level attain to
requirement voltage level L, output circuit stage operation is changed into SW driveNote2, and it stabilizes a voltage
level.
Since liquid crystal load is driven only by SW drive of γ-resistance direct file when referred to as AP = L before
attainment of the level to demand, most time is needed for level attainment.
Since this timing (AP = H period) is dependent on the load conditions of liquid crystal, it is a real use TFT panel and
fully needs to be evaluated.
Notes 1. When it is always set as AP = H, Sn pin starts an AMP drive automatically after the standup of 4 clock.
2. At the time of SW drive, stop the bias current of an output stage amplifier circuit, and stop the consumption
current of the output stage.
Preliminary Product Information S16240EJ1V0PM
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