UPD161831 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD161831

240/244-OUTPUT TFT-LCD SOURCE DRIVER WITH TIMING GENERATOR (COMPATIBLE WITH 64-GRAY SCALES)

NEC => Renesas Technology 

µPD161831

3.5 Control Pins when Timing Generator Function Not Used, and Other Pins

Pin Symbol

Pin Name

Pin Name I/O

Description

STHR

Right shift start 436

I/O Start pulse I/O pin during cascade connection. When an H level is read at

pulse I/O

the rising edge of CLK, fetching of display data starts.

STHL

Left shift start

509, 510

I/O In the case of right shift, STHR = input and STHL = output.

pulse I/O

In the case of left shift, STHL = input and STHR = output.

STB

Latch input

441

Input This is the timing signal at which the contents of the data register are

latched. When an H level is read at the rising edge of CLK, the contents of

the data register are latched and transferred to the D/A converter, and an

analog voltage is output according to the display data. Even after STB

fetch, do not stop CLK because the internal operation is performed using

CLK. At the rising edge of STB, the content of the shift register are

cleared. After one pulse is input at startup, the operation becomes normal.

At the rising edge of STB, the output switch is switched OFF. For the STB

input timing, refer to 5. TIMING GENERATOR NON-USE FUNCTION.

AP

Output SW

442

Input Switches the BIAS circuit ON/OFF and the output switch and amplifier ON.

ON/OFF

The period during which AP is H is the amplifier circuit setting period and

the liquid crystal drive period. At the falling edge of AP, the amplifier output

and output switch go ON and liquid crystal driving starts.

At the rising edge of STB, the output switch is switched to OFF ad the

output becomes Hi-Z.

POL

Polarity

443

inversion signal

Input Inverts the output polarity. At the siring edge of RSEL, the polarity inversion

signal data is fetched internally. The γ -resistor is switched according to the

positive and negative polarity.

POL = L: Negative polarity (common high output)

POL = H: Positive polarity (common low output)

3.6 Back Panel LCD Controller Driver Control Pins

Pin Symbol

Pin Name

Pin Name I/O

Description

/CS1

Back panel LCD 470

chip select

Output Active-low chip select signal to the back panel LCD controller driver.

CS2

Back panel LCD 469

Output Active-high chip select signal to the back panel LCD controller driver.

chip select

SCLK_SUB Serial clock to

471

the back panel

LCD

Output Back panel LCD serial data output.

SO_SUB

Outputs serial

472

data to the back

panel LCD

Output Outputs serial data to the back panel LCD controller driver.

A0

Back panel LCD 468

Output Controls data/command to the back panel LCD controller driver.

data/command

control

Preliminary Product Information S16269EJ2V0PM

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