UPD6376CX 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD6376CX

AUDIO 2-CHANNEL 16-BIT D/A CONVERTER

NEC => Renesas Technology 

µPD6376

2.1 Supplying Clock to CLK even outside Sample Data Interval

2.1.1 Serial data input (Pin 1 is Low or Open)

Synchronize the reverse timing of LRCK with the falling edge of CLK upon completion of LSB input (Point A in Figure

2-1).

Figure 2-1 Timing Chart for Serial Data Input

A

CLK

LSB

SI 16

A

Interval of 1 sample data

MSB

LSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MSB

1234

LRCK

2.1.2. Inputting parallel data (Pin 1 is High)

Synchronize the timing of the falling edge of WDCK with the falling edge of CLK upon completion of LSB input of

data (LSI, RSI) (Point A in Figure 2-2.).

Figure 2-2 Parallel Data Input Timing Chart

A

A

CLK

LSB

LSI 16

LSB

RSI 16

WDCK

MSB

LSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MSB

LSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MSB

12

MSB

12

6

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