UPD75236GJ 데이터 시트보기 (PDF) - NEC => Renesas Technology
부품명
상세내역
제조사
UPD75236GJ Datasheet PDF : 190 Pages
| |||
µPD75236
AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V)
(1) Basic operation
PARAMETER
CPU clock cycle time
(minimum instruction
execution time = 1
machine cycle) *1
TI0 input frequency
TI0 input high and low-
level widths
Interrupt input high and
low-level widths
RESET low-level width
SYMBOL
tCY
fTI
TEST CONDITIONS
Operation with main
system clock
VDD = 4.5 to 6.0 V
Operation with subsystem clock
VDD = 4.5 to 6.0 V
tTIH,
tTIL
tINTH,
tINTL
tRSL
VDD = 4.5 to 6.0 V
INT0
INT1, 2, 4
MIN.
0.95
3.8
114
0
0
0.48
1.8
*2
10
10
TYP. MAX. UNIT
64
µs
64
µs
122 125
µs
1
MHZ
275
kHz
µs
µs
µs
µs
µs
* 1. CPU clock (Φ) cycle time is determined by the
oscillator frequency of the connected resonator,
70
the system clock control register (SCC) and the
processor clock control register (PCC). The cycle
64
60
time tCY characteristics for power supply voltage
VDD when the main system clock is in operation
6
is shown below (see Fig.4-15 Processor Clock
5
Control Register Format).
4
2. 2tCY or 128/fX is set by interrupt mode register
(IM0) setting.
3
2
tCY VS VDD
(Main System Clock in Operation)
Operation Guaranteed
Range
1
0.5
0
1
2
3
4
5
6
Power Supply Voltage VDD [V]
175
Share Link: 