UPD75236GJ 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD75236GJ Datasheet PDF : 190 Pages
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µPD75236
(c) SBI mode (SCK...Internal clock output (master))
PARAMETER
SCK cycle time
SCK high and low level
widths
SB0 and SB1 setup time (to SCK↑)
SB0 and SB1 hold time (from SCK↑)
SB0 and SB1 output
delay time from SCK↓
SB0, SB1↓ from SCK↑
SCK from SB0, SB1↓
SB0 and SB1 low-level widths
SB0 and SB1 high-level widths
SYMBOL
tKCY3
tKL3
tKH3
tSIK3
tKSI3
tKSO3
tKSB
tSBK
tSBL
tSBH
TEST CONDITIONS
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
RL = 1 k Ω
CL = 100 pF*
VDD = 4.5 to 6.0 V
MIN. TYP. MAX. UNIT
1600
ns
3800
ns
tKCY/2-50
ns
tKCY/2-150
ns
150
ns
tKCY/2
0
ns
250
ns
0
1000
ns
tKCY
ns
tKCY
ns
tKCY
ns
tKCY
ns
* RL and CL are SO output line load resistance and load capacitance, respectively.
(d) SBI mode (SCK...External clock output (slave))
PARAMETER
SCK cycle time
SYMBOL
tKCY4
TEST CONDITIONS
VDD = 4.5 to 6.0 V
SCK high and low level
widths
SB0 and SB1 setup time (to SCK↑)
SB0 and SB1 hold time (from SCK↑)
SB0 and SB1 output
delay time from SCK↓
SB0, SB1↓ from SCK↑
SCK↓ from SB0, SB1↓
SB0 and SB1 low-level widths
SB0 and SB1 high-level widths
tKL4
tKH4
tSIK4
tKSI4
tKSO4
tKSB
tSBK
tSBL
tSBH
VDD = 4.5 to 6.0 V
RL = 1 k Ω
CL = 100 pF*
VDD = 4.5 to 6.0 V
MIN.
800
3200
400
1600
100
tKCY/2
0
0
tKCY
tKCY
tKCY
tKCY
TYP. MAX. UNIT
ns
ns
ns
ns
ns
ns
300
ns
1000
ns
ns
ns
ns
ns
* RL and CL are SO output line load resistance and load capacitance, respectively.
177
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