UPD754202GS 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD754202GS Datasheet PDF : 66 Pages
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µPD754202, 754202(A)
1. PIN CONFIGURATION (Top View)
• 20-pin plastic SOP (300 mil, 1.27-mm pitch)
µPD754202GS-×××-BA5
µPD754202GS(A)-×××-BA5
• 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
µPD754202GS-×××-GJG
µPD754202GS(A)-×××-GJG
RESET
1
X1
2
X2
3
VSS
4
IC
5
VDD
6
P60
7
P61/INT0
8
P62
9
P63
10
20
KRREN
19
P80
18
P30/PTO0
17
P31/PTO1
16
P32/PTO2
15
P33
14
P70/KR4
13
P71/KR5
12
P72/KR6
11
P73/KR7
IC: Internally Connected (Connect directly to VDD)
Pin Identification
IC
:
INT0
:
KR4 to KR7 :
KRREN
:
P30 to P33 :
P60 to P63 :
P70 to P73 :
P80
:
PTO0 to PTO2 :
RESET
:
VDD
:
VSS
:
X1, X2
:
Internally Connected
External Vectored Interrupt
Key Return 4 to 7
Key Return Reset Enable
Port 3
Port 6
Port 7
Port 8
Programmable Timer Output 0 to 2
Reset
Positive Power Supply
Ground
System Clock (Ceramic/Crystal)
6
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