µPD754202, 754202(A)
3.2 Non-port Pins
Pin Name
PTO0
PTO1
PTO2
INT0
KR4 to KR7
KRREN
X1
X2
RESET
IC
VDD
VSS
Input/Output
Alternate
Function
Function
I/O Circuit
After Reset
TypeNote
Output
Input
Input
Input
Input
–
P30
P31
P32
P61
P70 to P73
–
–
Timer counter output
Edge detection vectored
interrupt input (detected
edge is selectable)
Noise eliminator
selectable
Noise eliminator/
asynchronous
selectable
Falling edge detection testable input
Key return reset enable.
When KRREN = high level in STOP mode, reset
signal is generated at falling edge of KRn.
System clock oscillation crystal/ceramic
connection pin.
If using an external clock, input to X1 and reverse
input to X2.
Input
Input
Input
Input
–
E-B
F -A
B -A
B
–
Input
–
System reset input (low-level active).
Pull-up resistor can be incorporated on-chip
(mask option).
–
B -A
–
–
Internally connected. Connect directly to VDD.
–
–
–
–
Positive power supply
–
–
–
–
Ground potential
–
–
Note Circled characters indicate Schmitt trigger input.
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