UPD754264 데이터 시트보기 (PDF) - NEC => Renesas Technology

부품명

상세내역

제조사

UPD754264

4-BIT SINGLE-CHIP MICROCONTROLLERS

NEC => Renesas Technology 

µPD754264

4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE

4.1 Difference between Mk I and Mk II Modes

The µPD754264 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The

mode can be switched by the bit 3 of the Stack Bank Select register (SBS).

• Mk I mode:

• Mk II mode:

Instructions are compatible with the 75X Series. Can be used in the 75XL CPU with a ROM

capacity of up to 16 Kbytes.

Incompatible with 75X Series. Can be used in all the 75XL CPU’s including those products

whose ROM capacity is more than 16 Kbytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Number of stack bytes

for subroutine instructions

BRA !addr1 instruction

CALLA !addr1 instruction

CALL !addr instruction

CALLF !faddr instruction

2 bytes

Mk I Mode

Not available

3 machine cycles

2 machine cycles

Mk II Mode

3 bytes

Available

4 machine cycles

3 machine cycles

Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.

Therefore, this mode is effective for enhancing software compatibility with products that have a

program area of more than 16 Kbytes.

With regard to the number of stack bytes during execution of subroutine call instructions, the usable

area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.

However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes

longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and

processing performance than on software compatibility, the Mk I mode should be used.

11

Share Link: