µPD754264
3.2 Non-port Pins
Pin Name
PTO0
PTO1
PTO2
INT0
KR4 to KR7
AN0
AN1
KRREN
AVREF
X1
X2
RESET
IC
VDD
VSS
Input/Output
Output
Alternate
Function
P30
Function
Timer counter output pins
I/O Circuit
After Reset
TYPE Note 1
Input
E-B
P31
P32
Input
P61
Edge detection vectored Noise elimination
interrupt input pin
circuit can be
(detected edge can be
selected.
selected)
Asynchronous
Noise elimination circuit
input
can be selected.
Input
F -A
Input
P70 to P73 Falling edge detection testable input pins
Input
B -A
Input
P62
Analog signal input
Input
F -A
P63
Input
–
Key return reset enable pin
Input
B
The reset signal is generated at the falling edge
of KRn while KRREN is high in STOP mode.
Input
P60
A/D converter reference voltage
Input
F -A
Input
–
–
Crystal/ceramic resonator (for system clock
–
–
oscillation) connection pin
When inputting the external clock, input the
external clock to pin X1 and input the inverted
phase of the external clock to pin X2.
Input
–
System reset input pin (low-level active)
–
Pull-up resistor can be incorporated (mask option).
B -A
–
–
Internally Connected Connect directly to VDD.
–
–
–
–
Positive supply pin
–
–
–
–
Ground potential
–
–
Note Circled characters indicate the Schmitt-trigger input.
8