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UPD75518GF 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD75518GF
NEC
NEC => Renesas Technology NEC
UPD75518GF Datasheet PDF : 180 Pages
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µPD75518(A)
1.3 PIN INPUT/OUTPUT CIRCUITS
Fig. 1-1 shows the input/output circuit of each µPD75518(A) pin in a simplified manner.
Type A
Fig. 1-1 Pin Input/Output Circuits (1/3)
Type D
VDD
P-ch
IN
N-ch
Data
Output
disable
VDD
P-ch
OUT
N-ch
Type B
CMOS input buffer
Push-pull output which can be set to high-impedance output
(off for both P-ch and N-ch)
Type E
IN
Schmitt trigger input with hysteresis
Type B - C
VDD
P.U.R.
P-ch
P.U.R.
enable
IN
P.U.R.: Pull-Up Resistor
Schmitt trigger input with hysteresis
10
Data
Output
disable
Type D
IN/OUT
Type A
I/O circuit consisting of a push-pull output
of type D and an input buffer of type A
Type E - B
Output
disable
VDD
P.U.R.
P-ch
Data
Output
disable
Type D
IN/OUT
Type A
P.U.R.: Pull-Up Resistor

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