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UPD75518GF 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD75518GF
NEC
NEC => Renesas Technology NEC
UPD75518GF Datasheet PDF : 180 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
TI0/P13
PTO0/P20
BUZ/P23
Basic
interval
timer
INTBT
Timer/event
counter #0
INTT0
Watch timer
PPO/P80
SI0/SB1/P03
SO0/SB0/P02
SCK0/P01
SI1/P83
SO1/P82
SCK1/P81
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60
- KR7/P73
AN0 - AN3
AN4/P150
- AN7/P153
AVREF
AVSS
INTW
Timer/pulse
generator
INTTPG
Serial
interface 0
INTCSI
Serial
interface 1
Interrupt
control
Bit se-
quential
buffer (16)
A /D
converter
Program counter (15)
CY
SP(8)
ALU
SBS(2)
Bank
ROM program memory
32640 × 8 bits
General register
Decode and
control
RAM data memory
1024 × 4 bits
fX /2N
Clock output
control
Clock divider
Clock generator
Sub Main
Stand by
control
PCL /P22
XT1 XT2 X1 X2
CPU clock
Φ
RESET
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
4 P00 - P03
4 P10 - P13
4 P20 - P23
4 P30 - P33
4 P40 - P43 Note
4 P50 - P53 Note
4 P60 - P63
4 P70 - P73
4 P80 - P83
4 P90 - P93
4 P100 - P103
4 P110 - P113
4 P120 - P123 Note
4 P130 - P133 Note
4 P140 - P143 Note
4 P150 - P153
VDD VSS
Note Port 4, Port 5, Port 12, Port 13, and Port 14 are N-ch open-drain
I/O ports with a medium withstand voltage of 10 V.

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