UPD780957 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD780957

8-Bit Single-Chip Microcontrollers

NEC => Renesas Technology 

LIST OF FIGURES (1/5)

Figure No.

Title

Page

2-1 Recommended Connection Example of CAPH and CAPL (3-Time Division Bias Mode)..............................43

2-2 Recommended Connection Example of VLC1 and VLC2 (3-Time Division Bias Mode) ...................................44

2-3 Connection Example of VROUT0 and VROUT1 .................................................................................................44

2-4 Pin I/O Circuits .............................................................................................................................................47

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

3-10

Memory Map (for µPD780957(A)).................................................................................................................49

Memory Map (for µPD780958(A))................................................................................................................50

Data Memory Addressing (µPD780957(A))...................................................................................................53

Data Memory Addressing (µPD780958(A))...................................................................................................54

Format of Program Counter ..........................................................................................................................55

Format of Program Status Word ...................................................................................................................55

Format of Stack Pointer ................................................................................................................................57

Data Saved to Stack Memory .......................................................................................................................57

Data Restored from Stack Memory...............................................................................................................57

Format of General-Purpose Registers ..........................................................................................................58

4-1

4-2

4-3

4-4

4-5

4-6

4-7

4-8

4-9

4-10

4-11

4-12

4-13

4-14

4-15

4-16

4-17

4-18

Port Configuration .........................................................................................................................................76

Block Diagram of P00 to P06 ........................................................................................................................80

Block Diagram of P20 and P21 .....................................................................................................................81

Block Diagram of P22 to P27 ........................................................................................................................82

Block Diagram of P30, P32, and P35............................................................................................................83

Block Diagram of P31 and P37 .....................................................................................................................84

Block Diagram of P33, P34, and P36............................................................................................................85

Block Diagram of P40 to P47 ........................................................................................................................86

Block Diagram of P50 to P55 ........................................................................................................................87

Block Diagram of P56 and P57 .....................................................................................................................88

Block Diagram of P60 to P62 ........................................................................................................................89

Block Diagram of P63 to P67 ........................................................................................................................90

Block Diagram of P70 to P77 ........................................................................................................................91

Block Diagram of P80 to P87 ........................................................................................................................92

Block Diagram of P90 to P95 ........................................................................................................................93

Format of Port Mode Registers (PM0 and PM2 to PM9)...............................................................................95

Format of Pull-up Resistor Option Registers (PU0 and PU2 to PU9)............................................................97

Format of Port Function Control Registers (PF7 to PF9) ..............................................................................98

5-1 Block Diagram of Clock Generator..............................................................................................................102

5-2 Format of Processor Clock Control Register (PCC)....................................................................................104

5-3 Format of SUB2 Clock Control Register (CKC)...........................................................................................105

5-4 External Circuit of Main System Clock Oscillator ........................................................................................106

5-5 Examples of Incorrect Resonator Connection.............................................................................................107

5-6 External Circuit of Subsystem Clock 1 Oscillator ........................................................................................109

5-7 Examples of Incorrect Resonator Connection.............................................................................................109

18

User’s Manual U13655EJ2V1UD

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