NB85E 데이터 시트보기 (PDF) - NEC => Renesas Technology
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NB85E Datasheet PDF : 226 Pages
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8.1.1 Non-blocking load/store ....................................................................................................................168
8.1.2 2-clock branch ..................................................................................................................................169
8.1.3 Efficient pipeline processing .............................................................................................................170
8.2 Pipeline Flow During Execution of Instructions ..................................................................... 171
8.2.1 Load instructions...............................................................................................................................171
8.2.2 Store instructions ..............................................................................................................................172
8.2.3 Multiply instructions ..........................................................................................................................172
8.2.4 Arithmetic operation instructions.......................................................................................................173
8.2.5 Saturated operation instructions .......................................................................................................174
8.2.6 Logical operation instructions ...........................................................................................................174
8.2.7 Branch instructions ...........................................................................................................................174
8.2.8 Bit manipulation instructions .............................................................................................................176
8.2.9 Special instructions ...........................................................................................................................176
8.2.10 Debug function instructions...............................................................................................................181
8.3 Pipeline Disorder........................................................................................................................ 182
8.3.1 Alignment hazard..............................................................................................................................182
8.3.2 Referencing execution result of load instruction ...............................................................................183
8.3.3 Referencing execution result of multiply instruction ..........................................................................184
8.3.4 Referencing execution result of LDSR instruction for EIPC and FEPC.............................................185
8.3.5 Cautions when creating programs ....................................................................................................185
8.4 Additional Items Related to Pipeline ........................................................................................ 186
8.4.1 Harvard architecture .........................................................................................................................186
8.4.2 Short path .........................................................................................................................................187
CHAPTER 9 SHIFTING TO DEBUG MODE ...................................................................................... 189
9.1 How to Shift to Debug Mode ..................................................................................................... 189
9.2 Cautions ...................................................................................................................................... 195
APPENDIX A NOTES ............................................................................................................................ 197
A.1 Restriction on Conflict Between sld Instruction and Interrupt request ............................... 197
A.1.1 Description........................................................................................................................................197
A.1.2 Countermeasure ...............................................................................................................................197
APPENDIX B INSTRUCTION LIST...................................................................................................... 198
APPENDIX C INSTRUCTION OPCODE MAP.................................................................................... 212
APPENDIX D DIFFERENCES WITH ARCHITECTURE OF V850 CPU.......................................... 217
APPENDIX E INSTRUCTIONS ADDED FOR V850E1 CPU COMPARED WITH V850 CPU...... 219
APPENDIX F INDEX.............................................................................................................................. 221
APPENDIX G REVISION HISTORY..................................................................................................... 224
G.1 Major Revisions in This Edition................................................................................................ 224
G.2 History of Revisions up to This Edition ................................................................................... 225
User’s Manual U14559EJ3V1UM
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