CXA1854AR 데이터 시트보기 (PDF) - Sony Semiconductor

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CXA1854AR

Decoder/Driver/Timing Generator for Color LCD Panels

Sony Semiconductor 

CXA1854AR

Item

APL = 90%

Symbol

GAPL90

Conditions

Adjust the output amplitude at TP41 when SIG1 (APL:

50%) is input to (A) to 1.5Vp-p with V61. Assume this as

0 dB, and obtain the TP41 output amplitude ratio when

input SIG1 (APL: 90%) is input.

V3 = 2.5V, V60 = 3.5V

Min. Typ. Max. Unit

–4 –2.5 –1 dB

APL = 10%

GAPL10

Adjust the output amplitude at TP41 when SIG1 (APL:

50%) is input to (A) to 1.5Vp-p with V61. Assume this as

0dB, and obtain the TP41 output amplitude ratio when

input SIG1 (APL: 10%) is input.

V3 = 2.5V, V60 = 3.5V

1 2.5 4 dB

Contrast

Input SIG5 to (A) and obtain the ratio between the TP41

characteristics

GCNTMX output amplitude when V61 = 2.5V and the TP41 output

25

dB

MAX

amplitude when V61 = 5V.

Contrast

characteristics MIN GCNTMN

Input SIG5 to (A) and obtain the ratio between the TP41

output amplitude when V61 = 2.5V and the TP41 output

amplitude when V61 = 1V.

–10 –6 dB

Carrier leak

(residual carrier)

CRRLK

Input SIG3 (0dB) to (A) and (B). Adjust the chroma signal

phase so that the amplitude (black – white) at TP43 is at a

maximum. Using a spectrum analyzer, measure the input

and the 3.58MHz or 4.43MHz component, and obtain

CRRLK = 150mV × 10 ∆d/20 using their difference ∆d.

SW7 = A for NTSC measurement, and C for PAL

measurement.

30 mVpp

Y signal I/O delay

time

TDYYC

TDYCMN

TDYCMP

Input SIG6 (VL = 150mV) to (A).

Measure the delay time from the

rising edge of the input signal to the

rising edge of the non-reversed

output.

V5 = 2V

Y/C input

SW8 = C

Composite input

(NTSC)

Composite input

(PAL), SW7 = C

250 400 550 ns

630 780 930 ns

610 760 910 ns

– 14 –

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