VSC8164 데이터 시트보기 (PDF) - Vitesse Semiconductor
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VSC8164 Datasheet PDF : 16 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
Figure 7: Differential and Single Ended Input and Output Voltage Measurement
b
= α Single
Ended
a
Swing
b
= α Differential
Swing
a
* Differential swing (α) is specified as | b - a | ( or | a - b | ), as is the single ended swing.
Differential swing is specified as equal in magnitude to single ended swing.
Table 1: AC Characteristics
Parameters
Description
Min Max Units
Conditions
tpdd
Data valid from falling
edge of CLK16O+
0
800
ps.
tpd32
CLK32O transition from
falling edge of CLK16O+
0
1.0
ns.
tDR, tDF
D[15:0]+/- rise and fall
times
—
tCLKR, tCLKF
CLK16O+/- rise and fall
times
—
CLK16OD CLK16O+/- duty cycle
distortion
45
DI+ setup time with respect
tdsu
to falling edge of
100
HSCLKI+
tdh
DI+ hold time with respect
to falling edge of
75
HSCLKI+
HSCLKID HSCLKI+/- duty cycle
distortion
40
400
ps
20% to 80% into 50 Ohm load.
See Figure 7
250
ps
20% to 80% into 50 Ohm load.
See Figure 7
% of
55 clock High speed clock input at 2.488GHz
cycle
—
ps
—
ps
% of
60 clock
cycle
G52239-0, Rev. 3.3
5/17/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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