VSC8114QB 데이터 시트보기 (PDF) - Vitesse Semiconductor

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VSC8114QB

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

TXDATAOUT+

TXDATAOUT-

Figure 10: Transmit High Speed Data Timing Diagram

TTXDAT

Data Sheet

VSC8114

Table 5: Transmit High Speed Data Timing Table

Parameter

TTXDAT

Description

Transmit data width

Min

Typ

Max

-

1.608

-

Units

ns

TXLSCKOUT

TXLSCKIN

TXIN [7:0]

TXINP

TXPERR

Figure 11: Transmit Data Timing Diagram

TPROP

TCLKIN

TINSU

TINH

TERR

Table 6: Transmit Data Input Timing Table

Parameter

Description

TCLKIN

TINSU

Transmit data input byte clock period

Transmit data and parity setup time with respect to

TXLSCKIN

TINH

Transmit data and parity hold time with respect to

TXLSCKIN

TPROP

Maximum allowable propagation delay for connecting

TXLSCKOUT to TXLSCKIN

TERR

Propagation delay from TXLSCKIN to TXPERR

Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case

Min

Typ

Max

-

12.86

-

1.0

-

-

1.0

-

-

-

-

3.5

3.2

-

9.0

Units

ns

ns

ns

ns

ns

Page 10

© VITESSE SEMICONDUCTOR CORPORATION

G52185-0, Rev 4.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

11/1/99

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