VSC8124RE 데이터 시트보기 (PDF) - Vitesse Semiconductor

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VSC8124RE

2.488 Gb/s Quad Data Re-timer

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC8124

Table 4: AC Coupled High Speed Receiver Specifications

Parameter

∆V=Vh-Vl

Zin

Description

Input swing(1)

Differential input

impedance

Min

Typ

200

-

80

-

NOTE: 1) See Figure 8

Max

1200

120

Table 5: DC Coupled High Speed Receiver Specifications

Parameter

Description

Min

Typ

Max

Vcm

Vih

Vil

∆V=Vh-Vl

Input common mode

Input high level

Input low level

Input swing

-

VEE+0.9

VEE

200

0.43VCC

-

-

-

-

VCC-1.0

VCC-1.2

1200

2.488 Gb/s Quad

Data Re-timer

Units

mV

Ω

Conditions

Units

V

V

V

mV

Conditions

Table 6: REFCK Receiver Specifications

Parameter

Description

Min

Typ

Max

∆V=Vh-Vl

Input swing(1)

400

-

1300

Vcm

Input common

mode

1.27

-

1.49

Zin

Differential input

impedance

80

-

120

NOTE: 1) See Figure 8

Table 7: TTL Input (internal pull-down) Receiver Specifications

Parameter Description

Min

Typ

Max

Vih

Input high level

2000

-

-

Vil

Input low level

-

-

800

Iilh

Input leakage

current high

-

-

1

Iill

Input leakage

current low

-

-

1

Units

mV

V

Ω

Units

mV

mV

mA

mA

Table 8: TTL Output Driver Specifications

Parameter

Description

Min

Typ

Voh

Output high level

2400

-

Vol

Output low level

-

-

Max

-

400

Units

mV

mV

Conditions

Conditions

Vin = 3.3V

Vin = 0V

Conditions

G52271-0, Rev. 1.14

2/23/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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