PDU14F-100M 데이터 시트보기 (PDF) - Data Delay Devices

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PDU14F-100M

4-BIT PROGRAMMABLE DELAY LINE

Data Delay Devices 

DELAY LINE AUTOMATED TESTING

PDU14F

TEST CONDITIONS

INPUT:

Ambient Temperature: 25oC ± 3oC

Supply Voltage (Vcc): 5.0V ± 0.1V

Input Pulse:

High = 3.0V ± 0.1V

Low = 0.0V ± 0.1V

Source Impedance: 50Ω Max.

Rise/Fall Time:

3.0 ns Max. (measured

between 0.6V and 2.4V )

Pulse Width:

PWIN = 1.5 x Total Delay

Period:

PERIN = 4.5 x Total Delay

OUTPUT:

Load:

Cload:

Threshold:

1 FAST-TTL Gate

5pf ± 10%

1.5V (Rising & Falling)

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

COMPUTER

SYSTEM

PRINTER

PULSE

GENERATOR

OUT

TRIG

IN DEVICE UNDER OUT

TEST (DUT)

REF

IN

TRIG

TIME INTERVAL

COUNTER

Test Setup

TRISE

PWIN

PERIN

TFALL

INPUT

2.4V

VIH

2.4V

SIGNAL

1.5V

0.6V

1.5V

0.6V

VIL

TDAR

TDAF

OUTPUT

SIGNAL

VOH

1.5V

1.5V

VOL

Timing Diagram For Testing

Doc #97002

DATA DELAY DEVICES, INC.

5

1/13/97

3 Mt. Prospect Ave. Clifton, NJ 07013

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