25Q32VFIG 데이터 시트보기 (PDF) - Winbond

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25Q32VFIG

32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

Winbond 

W25Q32V

10.2.21 Erase Suspend (75h)

The Erase Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation

and then read from or program data to, any other sectors or blocks. The Erase Suspend instruction

sequence is shown in figure 21.

The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h) are not

allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If

written during the Chip Erase or Program operation, the Erase Suspend instruction is ignored.

The Erase Suspend instruction “75h” will be accepted by the device only if the SUS bit in the Status

Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase is on-going. If the SUS

bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A

maximum of time of “tSUS” (See AC Characteristics) is required to suspend the erase operation. The

BUSY bit in the Status Register will be cleared from 1 to 0 within “tSUS” and the SUS bit in the Status

Register will be set from 0 to 1 immediately after Erase Suspend. For a previously resumed Erase

operation, it is also required that the Suspend instruction “75h” is not issued earlier than a minimum of

time of “tSUS” following the preceding Resume instruction “7Ah”.

Unexpected power off during the Erase suspend state will reset the device and release the suspend

state. SUS bit in the Status Register will also reset to 0. The data within the sector or block that was being

suspended may become corrupted. It is recommended for the user to implement system design

techniques against the accidental power interruption and preserve data integrity during erase suspend

state.

Figure 21. Erase Suspend Instruction Sequence

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