W83176R-733 데이터 시트보기 (PDF) - Winbond
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W83176R-733 Datasheet PDF : 14 Pages
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W83176R-733/W83176G-733
DUAL BANK DDR BUFFER FOR VIA CHIPSET
Register 22: Slew Rate Control (Default: AAh), continued
BIT
NAME
PWD
DESCRIPTION
3 DDRBT/C2_SR<1>
1
DDRBT/C2 slew rate control bits
2 DDRBT/C2_SR<0>
0
1 DDRBT/C3_SR<1>
1
DDRBT/C3 slew rate control bits
0 DDRBT/C3_SR<0>
0
7.12 Register 23: Slew Rate Control (Default: AAh)
BIT
NAME
7 DDRBT/C4_SR<1>
6 DDRBT/C4_SR<0>
5 DDRBT/C5_SR<1>
4 DDRBT/C5_SR<0>
3 FBOUT_SR<1>
2 FBOUT_SR<0>
1 FAOUT_SR<1>
0 FAOUT_SR<0>
PWD
1
0
1
0
1
0
1
0
DESCRIPTION
DDRBT/C4 slew rate control bits
DDRBT/C5 slew rate control bits
FB_OUTB slew rate control bits
FB_OUTA slew rate control bits
Publication Release Date: March, 2006
-7-
Revision 1.0
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