WED3DL328V 데이터 시트보기 (PDF) - White Electronic Designs Corporation
부품명
상세내역
제조사
WED3DL328V Datasheet PDF : 27 Pages
| |||
White Electronic Designs
WED3DL328V
CURRENT STATE TRUTH TABLE (CONT.)
Current State
CE#
L
L
L
L
Refreshing
L
L
L
L
H
L
L
L
L
Mode Register
Accessing
L
L
L
L
H
RAS#
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
X
CAS#
L
L
H
H
L
L
H
H
X
L
L
H
H
L
L
H
H
X
Command
WE#
BA0-1
A11,
A10/AP-A0
L
OP Code
H
X
X
L
X
X
H
BA Row Address
L
BA
Column
H
BA
Column
L
X
X
H
X
X
X
X
X
L
OP Code
H
X
X
L
X
X
H
BA Row Address
L
BA
Column
H
BA
Column
L
X
X
H
X
X
X
X
X
Description
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Action
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after tRC
No Operation; Idle after tRC
No Operation; Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after two clock cycles
No Operation; Idle after two clock cycles
Notes
NOTES:
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to.
2. Both Banks must be idle otherwise it is an illegal action.
3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4. The Current State only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current Sate then
the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS# to CAS# Delay (tRCD) must occur before the command is given.
8. Address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satified.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June, 2002
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Share Link: 