WED3C7410E16M400BH9I 데이터 시트보기 (PDF) - White Electronic Designs Corporation

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WED3C7410E16M400BH9I

7410E RISC Microprocessor HiTCE™ Multichip Package

White Electronic Designs Corporation 

White Electronic Designs WED3C7410E16M-XBHX

PRELIMINARY

Table 1: L2CR Bit Settings

Bit

16

17

18

19

20

21

22

23

24–30

31

Name

Function

L2SL

L2 DLL slow. Setting L2SL increases the delay of each tap of the DLL delay line. It is intended to increase the delay through the DLL

to accommodate slower L2 RAM bus frequencies.

0: Setting for WED3C7410E16M-XBHX because L2 RAM interface is operated above 100 MHz.

L2DF

L2 differential clock. This mode supports the differential clock requirements of late-write SRAMs.

0: Setting for WED3C7410E16M-XBHX because late-write SRAMs are not used.

L2BYP L2 DLL bypass is reserved.

0: Setting for WED3C7410E16M-XBHX

L2FA

L2 flush assist (for software flush). When this bit is negated, all lines castout from the dL1 which have a state of CDMRSV=01xxx1

(i.e. C-bit negated), will not allocate in the L2 if they miss. Asserting this bit forces every castout from the dL1 to allocate an entry in

the L2 if that castout misses in the L2 regardless of the state of the C-bit. The L2FA bit must be set and the L2IO bit must be cleared

in order to use the software flush algorithm.

L2HWF

L2 hardware flush. When the processor detects the value of L2HWF set to 1, the L2 will begin a hardware flush. The flush will be

done by starting with low cache indices and increment these indices for way 0 of the cache, one index at a time until the maximum

index value is obtained. Then, the index will be cleared to zero and the same process is repeated for way 1 of the cache. For each

index and way of the cache, the processor will generate a castout operation to the system bus for all modified 32-byte sectors. At

the end of the hardware flush, all lines in the L2 tag will be invalidated. During the flush, all memory activity from the icache and

dcache are blocked from accessing the L2 until the flush is complete. Snoops, however, are fully serviced by the L2 during the flush.

When the L2 tags have been fully flushed of all valid entries, this bit will be reset to b’0" by hardware. When this bit is cleared, it

does not necessarily guarantee that all lines form the L2 have been written completely to the system interface. L2 copybacks can stll

be queued in the bus interface unit. Below is the code which must be run to use L2 Hardware Flush. When the final sync completes,

all modified lines in the L2 will have been written to the system address bus.

Disable interrupts

dssall

sync

set L2HWF

sync

L2IO

L2 Instruction-Only. Setting this bit enales instruction-only operation in the L2 cache. For this operation, only transactions from the

L1 instruction cache are allowed to be reloaded in the L2 cache. Data addresses already in the cache will still hit for the L1 data

cache. When both L2DO and L2IO are asserted, the L2 cache is effectively locked.

L2CLKSTP L2 Clock Stop. Setting this bit enables the automatic stopping of the L2CLK_OUT signals for cache rams that support this function.

While L2CLKSTP is set, the L2CLK_OUT signals will automatically be stopped when WED3C7410E16M-XBHX enters nap or sleep

mode, and automatically restarted when WED3C7410E16M-XBHX exits nap or sleep.

L2DRO

L2 DLL rollover. Setting this bit enables a potential rollover (or actual rollover) condition of the DLL to cause a checkstop for the

processor. A potential rollover condition occurs when the DLL is selecting the last tap of the delay line, and thus may risk rolling over

to the first tap with one adjustment while in the process of keeping synchronized. Such a condition is improper operation for the

DLL, and, while this condition is not expected, it allows detection for added security. This bit can be set when the DLL is first enabled

(set with the L2CLK bits) to detect rollover during initial synchronization. It could also be set when the L2 cache is enabled (with L2E

bit) after the DLL has achieved its initial lock.

-

Reserved

L2IP

L2 global invalidate in progress (read only)—See the Motorola user’s manual for L2 Invalidation procedure.

July 2004

Rev. 0

10

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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